fix(scripts): make Vivado TCL scripts portable and update RTL file lists

- Replace hardcoded /home/jason-stone/ paths with [info script]-relative
  path resolution in all 9 scripts (build17-21, insert_ila_probes,
  program_fpga, ila_capture, run_cdc_and_netlist)
- Point constraint references at tracked XDC files instead of
  untracked synth_only.xdc
- Remove six phantom RTL entries (chirp_lut_init.v, fft_1024_forward.v,
  fft_1024_inverse.v, level_shifter_interface.v, lvds_to_cmos_400m.v,
  usb_packet_analyzer.v)
- Add six existing modules to file lists (rx_gain_control.v,
  mti_canceller.v, cfar_ca.v, fpga_self_test.v, xfft_16.v,
  adc_clk_mmcm.v)

Closes #38

9_Firmware/9_2_FPGA/scripts/insert_ila_probes.tcl

@@ -32,9 +32,11 @@
 # 0. Configuration — all paths and parameters in one place
 # ==============================================================================
 
-set project_base   "/home/jason-stone/PLFM_RADAR_work/vivado_project"
+set script_dir     [file dirname [file normalize [info script]]]
+set project_root   [file normalize [file join $script_dir ".."]]
+set project_base   [file join $project_root "build"]
 set synth_dcp      "${project_base}/aeris10_radar.runs/synth_1/radar_system_top.dcp"
-set synth_xdc      "${project_base}/synth_only.xdc"
+set synth_xdc      [file join $project_root "constraints" "xc7a200t_fbg484.xdc"]
 set output_dir     "${project_base}/aeris10_radar.runs/impl_ila"
 set top_module     "radar_system_top"
 set part           "xc7a200tfbg484-2"