Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation

Bit-accurate Python model (fpga_model.py) mirrors full DDC RTL chain:
NCO -> mixer -> CIC -> FIR with exact fixed-point arithmetic matching
RTL DSP48E1 pipeline behavior including CREG=1 delay on CIC int_0.

Synthetic radar scene generator (radar_scene.py) produces ADC test
vectors for 5 scenarios: DC, single target (500m), multi-target (5),
noise-only, and 1 MHz sine wave.

DDC co-sim testbench (tb_ddc_cosim.v) feeds hex vectors through RTL
DDC and exports baseband I/Q to CSV. All 5 scenarios compile and run
with Icarus Verilog (iverilog -g2001 -DSIMULATION).

Comparison framework (compare.py) validates Python vs RTL using
statistical metrics (RMS ratio, DC offset, peak ratio) rather than
exact sample match due to RTL LFSR phase dithering. Results: 5/5 PASS.

9_Firmware/9_2_FPGA/tb/cosim/scenario_info.txt

@@ -0,0 +1,30 @@
+AERIS-10 Test Vector Scenarios
+============================================================
+
+System Parameters:
+  Carrier: 10.5 GHz
+  IF: 120 MHz
+  Chirp BW: 20 MHz
+  ADC: 400 MSPS, 8-bit
+  Range resolution: 7.5 m
+  Wavelength: 28.57 mm
+
+Scenario 1: Single target
+  Target(range=500.0m, vel=0.0m/s, RCS=0.0dBsm, delay=1333.3samp)
+
+Scenario 2: Multi-target (5 targets)
+  Target(range=100.0m, vel=0.0m/s, RCS=20.0dBsm, delay=266.7samp)
+  Target(range=500.0m, vel=30.0m/s, RCS=10.0dBsm, delay=1333.3samp)
+  Target(range=1000.0m, vel=-15.0m/s, RCS=5.0dBsm, delay=2666.7samp)
+  Target(range=2000.0m, vel=50.0m/s, RCS=0.0dBsm, delay=5333.3samp)
+  Target(range=5000.0m, vel=-5.0m/s, RCS=-5.0dBsm, delay=13333.3samp)
+
+Scenario 3: Noise only (stddev=5.0 LSB)
+
+Scenario 4: DC input (value=128)
+
+Scenario 5: 1 MHz sine wave (amplitude=50 LSB)
+
+Baseband MF test targets:
+  Target(range=500.0m, vel=0.0m/s, RCS=10.0dBsm, delay=1333.3samp)
+  Target(range=1500.0m, vel=20.0m/s, RCS=5.0dBsm, delay=4000.0samp)