Phase 1 hardware bring-up prep: ILA debug probes, CDC waivers, programming scripts
- Rename latency_buffer_2159 -> latency_buffer (module + file + all refs) - Add CDC waivers for 5 verified false-positive criticals to XDC - Add ILA debug probe insertion script (4 cores, 126 probe bits, 2 clock domains) - Add FPGA programming script (7-step flow with DONE pin verification) - Add ILA capture script (4 scenarios + health check, CSV export) - Add debug_ila.xdc with MARK_DEBUG fallback attributes - Full regression clean: 13/13 suites, 266/266 checks, 2048/2048 golden match
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################################################################################
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# insert_ila_probes.tcl
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#
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# AERIS-10 Radar FPGA — Post-Synthesis ILA Debug Core Insertion
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# Target: XC7A200T-2FBG484I
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# Design: radar_system_top (Build 13 frozen netlist)
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#
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# Usage:
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# vivado -mode batch -source insert_ila_probes.tcl
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#
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# This script:
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# 1. Opens the post-synth DCP from Build 13
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# 2. Inserts 4 ILA debug cores across 2 clock domains
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# 3. Runs full implementation with Build 13 directives
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# 4. Generates bitstream, reports, and .ltx probe file
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#
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# ILA 0: ADC Capture — 400 MHz (rx_inst/clk_400m) — 9 bits
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# ILA 1: DDC Output — 100 MHz (clk_100m_buf) — 37 bits
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# ILA 2: Matched Filter Out — 100 MHz (clk_100m_buf) — 35 bits
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# ILA 3: Doppler Output — 100 MHz (clk_100m_buf) — 45 bits
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#
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# Author: auto-generated for Jason Stone
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# Date: 2026-03-18
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################################################################################
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# ==============================================================================
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# 0. Configuration — all paths and parameters in one place
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# ==============================================================================
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set project_base "/home/jason-stone/PLFM_RADAR_work/vivado_project"
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set synth_dcp "${project_base}/aeris10_radar.runs/impl_1/radar_system_top.dcp"
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set synth_xdc "${project_base}/synth_only.xdc"
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set output_dir "${project_base}/aeris10_radar.runs/impl_ila"
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set top_module "radar_system_top"
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set part "xc7a200tfbg484-2"
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# Timestamp for output file naming
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set timestamp [clock format [clock seconds] -format {%Y%m%d_%H%M%S}]
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set run_tag "build13_ila_${timestamp}"
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# ILA parameters
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set ila_depth 4096
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set trigger_pos 512 ;# 512 pre-trigger samples
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# ==============================================================================
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# 1. Helper procedures
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# ==============================================================================
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# Resolve a net with fallback wildcard patterns. Returns the net object or
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# raises an error with diagnostic info if nothing is found.
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proc resolve_net {primary_pattern args} {
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# Try the primary pattern first
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set nets [get_nets -quiet $primary_pattern]
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if {[llength $nets] > 0} {
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puts "INFO: Resolved net '$primary_pattern' -> [lindex $nets 0]"
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return [lindex $nets 0]
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}
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# Try each fallback pattern
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foreach fallback $args {
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set nets [get_nets -quiet $fallback]
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if {[llength $nets] > 0} {
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puts "INFO: Primary '$primary_pattern' not found. Resolved via fallback '$fallback' -> [lindex $nets 0]"
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return [lindex $nets 0]
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}
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}
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# Nothing found — dump available nets in the hierarchy for diagnostics
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set hier_prefix [lindex [split $primary_pattern "/"] 0]
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puts "ERROR: Could not resolve net '$primary_pattern'"
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puts " Available nets under '${hier_prefix}/*' (first 40):"
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set nearby [get_nets -quiet -hierarchical "${hier_prefix}/*"]
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set count 0
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foreach n $nearby {
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puts " $n"
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incr count
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if {$count >= 40} { puts " ... (truncated)"; break }
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}
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error "Net resolution failed for '$primary_pattern'. See log above for nearby nets."
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}
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# Resolve a bus (vector) of nets. Returns a list of net objects.
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# pattern should contain %d which will be replaced with bit indices.
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# Example: resolve_bus "rx_inst/adc/adc_data_cmos\[%d\]" 7 0
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# tries bits 7 down to 0
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proc resolve_bus {pattern msb lsb args} {
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set net_list {}
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for {set i $msb} {$i >= $lsb} {incr i -1} {
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set bit_pattern [string map [list "%d" $i] $pattern]
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# Build fallback list for this bit
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set bit_fallbacks {}
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foreach fb $args {
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lappend bit_fallbacks [string map [list "%d" $i] $fb]
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}
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lappend net_list [resolve_net $bit_pattern {*}$bit_fallbacks]
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}
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return $net_list
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}
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# Connect a list of nets to an ILA probe port, creating additional probe ports
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# as needed. The first probe port (DATA) is already created by create_debug_core.
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# probe_index: starting probe port index (0 = use existing PROBE0)
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# Returns the next available probe index.
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proc connect_probe_nets {ila_name probe_index net_list probe_label} {
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set width [llength $net_list]
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puts "INFO: Connecting $width nets to ${ila_name}/probe${probe_index} ($probe_label)"
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if {$probe_index > 0} {
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create_debug_port $ila_name probe
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}
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set_property port_width $width [get_debug_ports ${ila_name}/probe${probe_index}]
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connect_debug_port ${ila_name}/probe${probe_index} $net_list
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return [expr {$probe_index + 1}]
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}
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# ==============================================================================
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# 2. Open the synthesized checkpoint
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# ==============================================================================
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puts "======================================================================"
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puts " AERIS-10 ILA Insertion — Starting at [clock format [clock seconds]]"
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puts "======================================================================"
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# Create output directory
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file mkdir $output_dir
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# Open the frozen Build 13 post-synth DCP
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puts "\nINFO: Opening post-synth DCP: $synth_dcp"
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open_checkpoint $synth_dcp
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# Verify the part
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set loaded_part [get_property PART [current_design]]
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puts "INFO: Design part = $loaded_part"
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if {$loaded_part ne $part} {
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puts "WARNING: Expected part '$part', got '$loaded_part'. Continuing anyway."
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}
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# Read the synthesis-only constraints (pin assignments, clocks, etc.)
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puts "INFO: Reading XDC: $synth_xdc"
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read_xdc $synth_xdc
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# ==============================================================================
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# 3. Verify clock nets exist before inserting ILA cores
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# ==============================================================================
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puts "\n--- Verifying clock nets ---"
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# 400 MHz clock — BUFG output inside ADC interface
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set clk_400m_net [resolve_net \
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"rx_inst/clk_400m" \
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"rx_inst/adc/clk_400m" \
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"rx_inst/ad9484_interface_400m_inst/clk_400m" \
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"rx_inst/*/O" \
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]
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# 100 MHz system clock — BUFG output
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set clk_100m_net [resolve_net \
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"clk_100m_buf" \
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"bufg_100m/O" \
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"clk_100m_BUFG" \
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]
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puts "INFO: 400 MHz clock net = $clk_400m_net"
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puts "INFO: 100 MHz clock net = $clk_100m_net"
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# ==============================================================================
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# 4. ILA 0 — ADC Capture (400 MHz domain)
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#
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# Monitors raw ADC data at the CMOS interface output.
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# 8-bit ADC data + 1-bit valid = 9 probed bits.
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# 4096 samples at 400 MHz => ~10.24 us capture window —
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# sufficient for one chirp segment observation.
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# ==============================================================================
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puts "\n====== ILA 0: ADC Capture (400 MHz) ======"
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create_debug_core u_ila_0 ila
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set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
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set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
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set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
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set_property C_DATA_DEPTH $ila_depth [get_debug_cores u_ila_0]
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set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0]
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set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
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set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
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set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
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# Clock: 400 MHz BUFG output from ADC interface
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set_property port_width 1 [get_debug_ports u_ila_0/clk]
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connect_debug_port u_ila_0/clk [get_nets $clk_400m_net]
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# Probe 0: adc_data_cmos[7:0] — raw 8-bit ADC sample from AD9484
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set adc_data_nets [resolve_bus \
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"rx_inst/adc/adc_data_cmos\[%d\]" 7 0 \
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"rx_inst/adc/adc_data_400m\[%d\]" \
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"rx_inst/ad9484_interface_400m_inst/adc_data_cmos\[%d\]" \
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"rx_inst/*/adc_data_cmos\[%d\]" \
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]
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set probe_idx 0
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set probe_idx [connect_probe_nets u_ila_0 $probe_idx $adc_data_nets "ADC raw data\[7:0\]"]
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# Probe 1: adc_valid — data valid strobe
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set adc_valid_net [resolve_net \
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"rx_inst/adc/adc_valid" \
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"rx_inst/ad9484_interface_400m_inst/adc_valid" \
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"rx_inst/*/adc_valid" \
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]
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set probe_idx [connect_probe_nets u_ila_0 $probe_idx [list $adc_valid_net] "ADC valid"]
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puts "INFO: ILA 0 configured — 9 probe bits on 400 MHz clock"
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# ==============================================================================
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# 5. ILA 1 — DDC Output (100 MHz domain)
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#
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# Monitors the digital down-converter output after CIC+FIR decimation.
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# 18-bit I + 18-bit Q + 1-bit valid = 37 probed bits.
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# With 4x decimation the effective sample rate is 25 MSPS,
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# so 4096 samples => ~163.8 us — covers multiple chirp periods.
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# ==============================================================================
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puts "\n====== ILA 1: DDC Output (100 MHz) ======"
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create_debug_core u_ila_1 ila
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set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_1]
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set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_1]
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set_property C_ADV_TRIGGER false [get_debug_cores u_ila_1]
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set_property C_DATA_DEPTH $ila_depth [get_debug_cores u_ila_1]
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set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_1]
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set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_1]
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set_property C_TRIGIN_EN false [get_debug_cores u_ila_1]
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set_property C_TRIGOUT_EN false [get_debug_cores u_ila_1]
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# Clock: 100 MHz system clock
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set_property port_width 1 [get_debug_ports u_ila_1/clk]
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connect_debug_port u_ila_1/clk [get_nets $clk_100m_net]
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# Probe 0: ddc_out_i[17:0] — DDC I-channel baseband output
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set ddc_i_nets [resolve_bus \
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"rx_inst/ddc_out_i\[%d\]" 17 0 \
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"rx_inst/ddc_400m_inst/ddc_out_i\[%d\]" \
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"rx_inst/*/ddc_out_i\[%d\]" \
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]
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set probe_idx 0
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set probe_idx [connect_probe_nets u_ila_1 $probe_idx $ddc_i_nets "DDC I\[17:0\]"]
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# Probe 1: ddc_out_q[17:0] — DDC Q-channel baseband output
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set ddc_q_nets [resolve_bus \
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"rx_inst/ddc_out_q\[%d\]" 17 0 \
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"rx_inst/ddc_400m_inst/ddc_out_q\[%d\]" \
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"rx_inst/*/ddc_out_q\[%d\]" \
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]
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set probe_idx [connect_probe_nets u_ila_1 $probe_idx $ddc_q_nets "DDC Q\[17:0\]"]
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# Probe 2: ddc_valid_i — DDC output valid strobe (I path; Q valid assumed coincident)
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set ddc_valid_net [resolve_net \
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"rx_inst/ddc_valid_i" \
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"rx_inst/ddc_400m_inst/ddc_valid_i" \
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"rx_inst/*/ddc_valid_i" \
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"rx_inst/ddc_valid" \
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]
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set probe_idx [connect_probe_nets u_ila_1 $probe_idx [list $ddc_valid_net] "DDC valid"]
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puts "INFO: ILA 1 configured — 37 probe bits on 100 MHz clock"
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# ==============================================================================
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# 6. ILA 2 — Matched Filter Output (100 MHz domain)
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#
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# Monitors the pulse-compression matched filter output.
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# 16-bit I + 16-bit Q + 1-bit valid + 2-bit segment index = 35 probed bits.
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# This allows verifying correct chirp segment correlation and range profile.
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# ==============================================================================
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puts "\n====== ILA 2: Matched Filter Output (100 MHz) ======"
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create_debug_core u_ila_2 ila
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set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_2]
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set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_2]
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set_property C_ADV_TRIGGER false [get_debug_cores u_ila_2]
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set_property C_DATA_DEPTH $ila_depth [get_debug_cores u_ila_2]
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set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_2]
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set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_2]
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set_property C_TRIGIN_EN false [get_debug_cores u_ila_2]
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set_property C_TRIGOUT_EN false [get_debug_cores u_ila_2]
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# Clock: 100 MHz system clock (shared with ILA 1)
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set_property port_width 1 [get_debug_ports u_ila_2/clk]
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connect_debug_port u_ila_2/clk [get_nets $clk_100m_net]
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# Probe 0: pc_i_w[15:0] — matched filter range-compressed I output
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set mf_i_nets [resolve_bus \
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"rx_inst/mf_dual/pc_i_w\[%d\]" 15 0 \
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"rx_inst/matched_filter_multi_segment_inst/pc_i_w\[%d\]" \
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"rx_inst/*/pc_i_w\[%d\]" \
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]
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set probe_idx 0
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set probe_idx [connect_probe_nets u_ila_2 $probe_idx $mf_i_nets "MF I\[15:0\]"]
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# Probe 1: pc_q_w[15:0] — matched filter range-compressed Q output
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set mf_q_nets [resolve_bus \
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"rx_inst/mf_dual/pc_q_w\[%d\]" 15 0 \
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"rx_inst/matched_filter_multi_segment_inst/pc_q_w\[%d\]" \
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"rx_inst/*/pc_q_w\[%d\]" \
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]
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set probe_idx [connect_probe_nets u_ila_2 $probe_idx $mf_q_nets "MF Q\[15:0\]"]
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# Probe 2: pc_valid_w — matched filter output valid
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set mf_valid_net [resolve_net \
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"rx_inst/mf_dual/pc_valid_w" \
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"rx_inst/matched_filter_multi_segment_inst/pc_valid_w" \
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"rx_inst/*/pc_valid_w" \
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]
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set probe_idx [connect_probe_nets u_ila_2 $probe_idx [list $mf_valid_net] "MF valid"]
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# Probe 3: segment_request[1:0] — chirp segment being correlated (0-3)
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set seg_nets [resolve_bus \
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"rx_inst/mf_dual/segment_request\[%d\]" 1 0 \
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"rx_inst/matched_filter_multi_segment_inst/segment_request\[%d\]" \
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"rx_inst/*/segment_request\[%d\]" \
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]
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set probe_idx [connect_probe_nets u_ila_2 $probe_idx $seg_nets "MF segment\[1:0\]"]
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puts "INFO: ILA 2 configured — 35 probe bits on 100 MHz clock"
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# ==============================================================================
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# 7. ILA 3 — Doppler Output (100 MHz domain)
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#
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# Monitors the Doppler processor output (post-FFT).
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# 32-bit spectrum + 1-bit valid + 5-bit Doppler bin + 6-bit range bin
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# + 1-bit frame sync = 45 probed bits.
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# Allows verification of the range-Doppler map generation.
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# ==============================================================================
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puts "\n====== ILA 3: Doppler Output (100 MHz) ======"
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create_debug_core u_ila_3 ila
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set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_3]
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set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_3]
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set_property C_ADV_TRIGGER false [get_debug_cores u_ila_3]
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set_property C_DATA_DEPTH $ila_depth [get_debug_cores u_ila_3]
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set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_3]
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set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_3]
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set_property C_TRIGIN_EN false [get_debug_cores u_ila_3]
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set_property C_TRIGOUT_EN false [get_debug_cores u_ila_3]
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# Clock: 100 MHz system clock (shared with ILA 1, ILA 2)
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set_property port_width 1 [get_debug_ports u_ila_3/clk]
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connect_debug_port u_ila_3/clk [get_nets $clk_100m_net]
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# Probe 0: doppler_output[31:0] — Doppler FFT magnitude/spectrum output
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set dop_out_nets [resolve_bus \
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"rx_inst/doppler_proc/doppler_output\[%d\]" 31 0 \
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"rx_inst/doppler_processor_inst/doppler_output\[%d\]" \
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"rx_inst/*/doppler_output\[%d\]" \
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]
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set probe_idx 0
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set probe_idx [connect_probe_nets u_ila_3 $probe_idx $dop_out_nets "Doppler spectrum\[31:0\]"]
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# Probe 1: doppler_valid — Doppler output valid strobe
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set dop_valid_net [resolve_net \
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"rx_inst/doppler_proc/doppler_valid" \
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"rx_inst/doppler_processor_inst/doppler_valid" \
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"rx_inst/*/doppler_valid" \
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]
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set probe_idx [connect_probe_nets u_ila_3 $probe_idx [list $dop_valid_net] "Doppler valid"]
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# Probe 2: doppler_bin[4:0] — Doppler frequency bin index (0-31)
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set dop_bin_nets [resolve_bus \
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"rx_inst/doppler_proc/doppler_bin\[%d\]" 4 0 \
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"rx_inst/doppler_processor_inst/doppler_bin\[%d\]" \
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"rx_inst/*/doppler_bin\[%d\]" \
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]
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set probe_idx [connect_probe_nets u_ila_3 $probe_idx $dop_bin_nets "Doppler bin\[4:0\]"]
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|
||||
# Probe 3: range_bin[5:0] — range bin index (0-63)
|
||||
set rng_bin_nets [resolve_bus \
|
||||
"rx_inst/doppler_proc/range_bin\[%d\]" 5 0 \
|
||||
"rx_inst/doppler_processor_inst/range_bin\[%d\]" \
|
||||
"rx_inst/*/range_bin\[%d\]" \
|
||||
]
|
||||
set probe_idx [connect_probe_nets u_ila_3 $probe_idx $rng_bin_nets "Range bin\[5:0\]"]
|
||||
|
||||
# Probe 4: new_frame_pulse — top-level frame synchronization pulse
|
||||
set frame_net [resolve_net \
|
||||
"rx_inst/new_frame_pulse" \
|
||||
"rx_inst/radar_receiver_final_inst/new_frame_pulse" \
|
||||
"rx_inst/*/new_frame_pulse" \
|
||||
"new_frame_pulse" \
|
||||
]
|
||||
set probe_idx [connect_probe_nets u_ila_3 $probe_idx [list $frame_net] "Frame sync pulse"]
|
||||
|
||||
puts "INFO: ILA 3 configured — 45 probe bits on 100 MHz clock"
|
||||
|
||||
# ==============================================================================
|
||||
# 8. Implement the modified design
|
||||
# ==============================================================================
|
||||
|
||||
puts "\n======================================================================"
|
||||
puts " Implementation — matching Build 13 directives"
|
||||
puts "======================================================================"
|
||||
|
||||
# Save the post-ILA-insertion checkpoint for reference
|
||||
set ila_dcp "${output_dir}/${top_module}_ila_inserted.dcp"
|
||||
write_checkpoint -force $ila_dcp
|
||||
puts "INFO: Saved ILA-inserted checkpoint: $ila_dcp"
|
||||
|
||||
# --- opt_design (Explore) ---
|
||||
puts "\n--- opt_design -directive Explore ---"
|
||||
opt_design -directive Explore
|
||||
|
||||
write_checkpoint -force "${output_dir}/${top_module}_opt.dcp"
|
||||
|
||||
# --- place_design (ExtraTimingOpt) ---
|
||||
puts "\n--- place_design -directive ExtraTimingOpt ---"
|
||||
place_design -directive ExtraTimingOpt
|
||||
|
||||
write_checkpoint -force "${output_dir}/${top_module}_placed.dcp"
|
||||
|
||||
# Post-place timing estimate
|
||||
report_timing_summary -file "${output_dir}/timing_post_place.rpt" -max_paths 20
|
||||
|
||||
# --- phys_opt_design (AggressiveExplore) — post-place ---
|
||||
puts "\n--- phys_opt_design -directive AggressiveExplore (post-place) ---"
|
||||
phys_opt_design -directive AggressiveExplore
|
||||
|
||||
write_checkpoint -force "${output_dir}/${top_module}_physopt.dcp"
|
||||
|
||||
# --- route_design (AggressiveExplore) ---
|
||||
puts "\n--- route_design -directive AggressiveExplore ---"
|
||||
route_design -directive AggressiveExplore
|
||||
|
||||
write_checkpoint -force "${output_dir}/${top_module}_routed.dcp"
|
||||
|
||||
# Post-route timing check
|
||||
report_timing_summary -file "${output_dir}/timing_post_route.rpt" -max_paths 50
|
||||
|
||||
# --- post-route phys_opt_design (AggressiveExplore) ---
|
||||
puts "\n--- phys_opt_design -directive AggressiveExplore (post-route) ---"
|
||||
phys_opt_design -directive AggressiveExplore
|
||||
|
||||
# Final routed + physopt checkpoint
|
||||
set final_dcp "${output_dir}/${top_module}_postroute_physopt.dcp"
|
||||
write_checkpoint -force $final_dcp
|
||||
puts "INFO: Final checkpoint: $final_dcp"
|
||||
|
||||
# ==============================================================================
|
||||
# 9. Generate reports for comparison with Build 13
|
||||
# ==============================================================================
|
||||
|
||||
puts "\n======================================================================"
|
||||
puts " Reports"
|
||||
puts "======================================================================"
|
||||
|
||||
# Timing summary (compare WNS/TNS/WHS/THS against Build 13)
|
||||
report_timing_summary \
|
||||
-file "${output_dir}/timing_summary_final.rpt" \
|
||||
-max_paths 100 \
|
||||
-report_unconstrained
|
||||
|
||||
# Per-clock-domain timing (critical for multi-clock radar design)
|
||||
report_timing \
|
||||
-file "${output_dir}/timing_per_clock.rpt" \
|
||||
-max_paths 20 \
|
||||
-sort_by group
|
||||
|
||||
# Utilization (expect ~2-4% increase from ILA cores on XC7A200T)
|
||||
report_utilization \
|
||||
-file "${output_dir}/utilization.rpt"
|
||||
|
||||
report_utilization \
|
||||
-file "${output_dir}/utilization_hierarchical.rpt" \
|
||||
-hierarchical
|
||||
|
||||
# DRC
|
||||
report_drc \
|
||||
-file "${output_dir}/drc.rpt"
|
||||
|
||||
# Clock interaction / CDC (important with 400 MHz <-> 100 MHz crossing)
|
||||
report_clock_interaction \
|
||||
-file "${output_dir}/clock_interaction.rpt" \
|
||||
-delay_type min_max
|
||||
|
||||
# Clock networks (verify BUFG usage)
|
||||
report_clock_networks \
|
||||
-file "${output_dir}/clock_networks.rpt"
|
||||
|
||||
# Power estimate
|
||||
report_power \
|
||||
-file "${output_dir}/power.rpt"
|
||||
|
||||
# ILA core summary
|
||||
report_debug_core \
|
||||
-file "${output_dir}/debug_core_summary.rpt"
|
||||
|
||||
puts "INFO: All reports written to $output_dir"
|
||||
|
||||
# ==============================================================================
|
||||
# 10. Write debug probes file (.ltx) for Vivado Hardware Manager
|
||||
# ==============================================================================
|
||||
|
||||
puts "\n--- Writing debug probes .ltx file ---"
|
||||
|
||||
set ltx_file "${output_dir}/${top_module}.ltx"
|
||||
write_debug_probes -force $ltx_file
|
||||
puts "INFO: Debug probes file: $ltx_file"
|
||||
|
||||
# Also copy the .ltx next to the bitstream for convenience
|
||||
file copy -force $ltx_file "${output_dir}/debug_nets.ltx"
|
||||
|
||||
# ==============================================================================
|
||||
# 11. Generate bitstream
|
||||
# ==============================================================================
|
||||
|
||||
puts "\n======================================================================"
|
||||
puts " Bitstream Generation"
|
||||
puts "======================================================================"
|
||||
|
||||
set bitstream_file "${output_dir}/${top_module}.bit"
|
||||
|
||||
write_bitstream -force $bitstream_file
|
||||
|
||||
puts "INFO: Bitstream written: $bitstream_file"
|
||||
|
||||
# Also generate a .bin file for SPI flash programming if needed
|
||||
write_cfgmem -force \
|
||||
-format BIN \
|
||||
-size 32 \
|
||||
-interface SPIx4 \
|
||||
-loadbit "up 0x0 $bitstream_file" \
|
||||
"${output_dir}/${top_module}.bin"
|
||||
|
||||
puts "INFO: SPI flash image: ${output_dir}/${top_module}.bin"
|
||||
|
||||
# ==============================================================================
|
||||
# 12. Final summary
|
||||
# ==============================================================================
|
||||
|
||||
puts "\n======================================================================"
|
||||
puts " AERIS-10 ILA Insertion Complete"
|
||||
puts "======================================================================"
|
||||
puts ""
|
||||
puts " Output directory: $output_dir"
|
||||
puts " Final DCP: $final_dcp"
|
||||
puts " Bitstream: $bitstream_file"
|
||||
puts " Debug probes: $ltx_file"
|
||||
puts " Run tag: $run_tag"
|
||||
puts ""
|
||||
puts " ILA Cores Inserted:"
|
||||
puts " u_ila_0 : ADC Capture (400 MHz, 9 bits, depth=$ila_depth)"
|
||||
puts " u_ila_1 : DDC Output (100 MHz, 37 bits, depth=$ila_depth)"
|
||||
puts " u_ila_2 : Matched Filter (100 MHz, 35 bits, depth=$ila_depth)"
|
||||
puts " u_ila_3 : Doppler Output (100 MHz, 45 bits, depth=$ila_depth)"
|
||||
puts ""
|
||||
puts " Compare these reports against Build 13 baseline:"
|
||||
puts " - timing_summary_final.rpt (WNS/TNS/WHS/THS)"
|
||||
puts " - utilization.rpt (BRAM/LUT/FF overhead)"
|
||||
puts " - clock_interaction.rpt (CDC paths)"
|
||||
puts ""
|
||||
puts " To load in Hardware Manager:"
|
||||
puts " 1. Program bitstream: $bitstream_file"
|
||||
puts " 2. Load probes file: $ltx_file"
|
||||
puts " 3. Set trigger position to $trigger_pos for pre/post capture"
|
||||
puts ""
|
||||
puts " Finished at [clock format [clock seconds]]"
|
||||
puts "======================================================================"
|
||||
|
||||
close_design
|
||||
Reference in new issue
Block a user