 Jason
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463ebef554
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CIC comb pipeline registers, BUFG sim guard, system TB fix, regression runner
- cic_decimator_4x_enhanced.v: Add integrator_sampled_comb and
data_valid_comb_pipe pipeline stages between integrator sampling and
comb computation to break the critical path (matches remote 40cda0f)
- radar_system_top.v: Wrap 3 BUFG instances in ifdef SIMULATION guard
with pass-through assigns for iverilog compatibility
- radar_system_tb.v: Convert generate_radar_echo function to task and
move sin_lut declaration before task (iverilog declaration-order fix),
add modular index clamping to prevent LUT out-of-bounds
- run_regression.sh: Automated regression runner for all 18 FPGA
testbenches with --quick mode. Results: 17 pass, 1 pre-existing fail
- .gitignore: Exclude *.vvp, *.vcd simulation artifacts
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2026-03-19 11:31:46 +02:00 |
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Jason
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a9c857c447
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Remove 15 dead files, move radar_system_tb.v to tb/ directory
Dead modules removed (7 tracked, 8 untracked debug files):
- fft_1024_forward.v, fft_1024_inverse.v (wrap non-existent IP)
- lvds_to_cmos_400m.v, level_shifter_interface.v (unused)
- chirp_lut_init.v (orphan initial block)
- usb_packet_analyzer.v (never instantiated)
- debug_fft*.v x8 (standalone debug scripts)
- cntrt.xdc (stale duplicate of upstream XDC)
Moved radar_system_tb.v from root to tb/ (correct location).
All regression tests pass: integration 10/10, Doppler 14/14, MF 3/3.
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2026-03-17 01:08:26 +02:00 |
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