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b3608ecfd7dd02565bbfde037f92c1e65a3d86d7
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13 Commits

Author SHA1 Message Date
thebadking
b3608ecfd7 Rename the simulator to Overwatch and organize the repository for presentation.
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The operator interface now uses that name. The radar design, parts list, and simulation sit in separate directories, and the earlier simulator and project license are removed.

Co-authored-by: Cursor <cursoragent@cursor.com>
 2026-10-21 06:04:46 +00:00
Jason
d5d28e9f1c Build 25 engineering report: MTI canceller + DC notch timing PASS 
Build 25 results (MTI + DC notch integration):
- WNS +0.132 ns, WHS +0.058 ns (all domains PASS)
- 9,252 LUTs, 12,488 FFs, 17 BRAM, 142 DSP, 0.753 W
- MTI cost: +694 LUTs, +2,104 FFs, 0 BRAM, 0 DSP
- Bitstream: radar_system_top_build25.bit (production-safe)
- 23/23 FPGA regression, 29/29 MTI checks, 3/3 real-data co-sim

Updated reports.html (15-point Build 25 report), implementation-log.html
(timeline entries for production fixes, CFAR, MTI), and release-notes.html
(new tagged releases, gap status update).
 2026-03-20 16:59:30 +02:00
Jason
075ae1e77a Add Build 24 15-point engineering report: timing, utilization, DSP/BRAM breakdown, power, DRC, methodology, congestion, routing, logic levels, build comparison, CFAR cost, verification summary 2026-03-20 05:47:20 +02:00
Jason
19284ac277 Build 21 docs + TCL fix: WNS +0.156ns, 139 DSP, tag v0.1.4-build21 
Build 21 Vivado results extracted and documented:
- WNS +0.156 ns, WHS +0.064 ns, WPWS +0.361 ns (all timing met)
- 6,192 LUTs (4.6%), 9,064 FFs (3.4%), 16 BRAM (4.4%), 139 DSP48E1 (18.8%)
- Total power: 0.732 W
- Barrel-shift twiddle freed 1 DSP (140 -> 139) as expected
- TCL script fix: wrap check_timing in catch (Vivado 2025.2 bug)
- Updated release-notes.html, implementation-log.html, reports.html
 2026-03-20 02:21:33 +02:00
Jason
a31b4ec484 Update docs for FFT optimizations + E2E test + RTL fixes (19/19 FPGA regression) 2026-03-20 01:46:24 +02:00
Jason
02b3b68e00 Update docs for Gap 2 GUI Settings completion (5 of 7 gaps closed) 2026-03-19 23:58:37 +02:00
Jason
d2f20f5c15 Update docs for Build 20 (v0.1.3-build20) stable release + Gaps 3-7 status 
- release-notes.html: Add commits for Gaps 3-5-7-4, tagged releases table,
  architectural gap status table, updated GitHub links
- implementation-log.html: Add Build 20/19/18 timeline entries, Gap 3-4-5
  milestones, updated quality/build history sections
- reports.html: Update FPGA status to Build 20 baseline, MCU regression
  to 20/20, report currency notice with current gap status
 2026-03-19 23:22:38 +02:00
Jason
f16d9524e5 Add board-day worksheet and cross-link bring-up docs 2026-03-19 15:25:23 +02:00
Jason
e62f3cd950 Port validated Build 16 XDC cleanup and sync docs 2026-03-19 14:34:26 +02:00
Jason
3755ee6302 Publish Simulation Report v2 aligned to current FPGA baseline 2026-03-18 21:51:08 +02:00
Jason
5710f7a83e Annotate report currency status and flag legacy simulation PDF 2026-03-18 21:46:52 +02:00
Jason
cad804c347 Add release notes page keyed to major bring-up commits 2026-03-18 21:41:56 +02:00
Jason
94eed1e933 Expand GitHub Pages into full engineering documentation site 2026-03-18 21:40:44 +02:00