2 Commits

Author	SHA1	Message	Date
Jason	5499827ab7	add TE0713+UMFT601X-B FT601 integration dev bitstream (timing clean) ... FMC LPC dev build for TE0713/TE0701 + UMFT601X-B stack. Fixed timing closure: replaced set_output_delay with set_max_delay -datapath_only to eliminate false IBUF+BUFG clock skew penalty on source-synchronous outputs. Removed erroneous set_input_delay on output-only ft601_be[*]. Added IOB packing for siwu_n, false paths for async GPIO/reset/wakeup. Strategy: Performance_ExplorePostRoutePhysOpt. Results: WNS +0.059 ns, WHS +0.121 ns, DRC 0 errors, 0 failing endpoints. Bitstream: docs/artifacts/te0713-te0701-umft601x-dev-2026-03-21.bit	2026-03-21 20:43:52 +02:00
Jason	9b786eb33f	Add FMC-path FT601 XDC for TE0713+TE0701+UMFT601X-B pin mapping ... Maps all 47 FT601 signals through FMC LPC J10 to correct FPGA pins: - DATA[31:0] + D_CLK: Bank 15 (LA17-LA33) - BE_N[3:0], control, status: Bank 16 (LA00-LA15) Both banks share VIOTB rail — set to 3.3V for LVCMOS33. Includes timing constraints and RTL adaptation notes.	2026-03-19 16:20:56 +02:00