2 Commits

Author	SHA1	Message	Date
Jason	0773001708	E2E integration test + RTL fixes: mixer sequencing, USB data-pending flags, receiver toggle wiring (19/19 FPGA) ... RTL fixes discovered via new end-to-end testbench: - plfm_chirp_controller: TX/RX mixer enables now mutually exclusive by FSM state (Fix #4), preventing simultaneous TX+RX activation - usb_data_interface: stream control reset default 3'b001 (range-only), added doppler/cfar data_pending sticky flags, write FSM triggers on range_valid only — eliminates startup deadlock (Fix #5) - radar_receiver_final: STM32 toggle signals wired through for mode-00 pass-through, dynamic frame detection via host_chirps_per_elev - radar_system_top: STM32 toggle signal wiring to receiver instance - chirp_memory_loader_param: explicit readmemh range for short chirp Test infrastructure: - New tb_system_e2e.v: 46 checks across 12 groups (reset, TX, safety, RX, USB R/W, CDC, beam scanning, reset recovery, stream control, latency budgets, watchdog) - tb_usb_data_interface: Tests 21/22/56 updated for data_pending architecture (preload flags, verify consumption instead of state) - tb_chirp_controller: mixer tests T7.1/T7.2 updated for Fix #4 - run_regression.sh: PASS/FAIL regex fixed to match only [PASS]/[FAIL] markers, added E2E test entry - Updated rx_final_doppler_out.csv golden data	2026-03-20 01:45:00 +02:00
Jason	558f49cd4a	Add 8 Verilog testbenches with full coverage (144/144 pass) ... Testbenches for: edge_detector (17), nco_400m (20), cic_decimator (14), fir_lowpass (13), freq_matched_filter (14), ddc_400m full-chain (7), chirp_controller (39), chirp_contract regression (20). Includes CSV output data for waveform verification. Add .gitignore to exclude VCD/VVP build artifacts.	2026-03-15 06:14:11 +02:00