2 Commits

Include renames

Author	SHA1	Message	Date
Jason	ed6f79c6d3	FIR DSP48 pipelining (BREG+MREG) + matched filter BRAM migration with overlap cache ... FIR: Add coeff_reg/mult_reg pipeline stages to fix 68 DPIP-1 + 35 DPOP-2 DRC warnings. Valid pipeline widened 7→9 bits (+2 cycle latency). Matched filter: Migrate input_buffer_i/q from register arrays to BRAM (~33K FF savings). Overlap-save uses register cache captured during ST_PROCESSING to avoid BRAM read/write conflicts during overlap copy. New ST_OVERLAP_COPY state writes cached tail samples back sequentially. Both changes pass 18/18 FPGA regression. Golden data regenerated for +2 FIR latency baseline.	2026-03-19 20:39:01 +02:00
Jason	558f49cd4a	Add 8 Verilog testbenches with full coverage (144/144 pass) ... Testbenches for: edge_detector (17), nco_400m (20), cic_decimator (14), fir_lowpass (13), freq_matched_filter (14), ddc_400m full-chain (7), chirp_controller (39), chirp_contract regression (20). Includes CSV output data for waveform verification. Add .gitignore to exclude VCD/VVP build artifacts.	2026-03-15 06:14:11 +02:00