19284ac277
Build 21 Vivado results extracted and documented: - WNS +0.156 ns, WHS +0.064 ns, WPWS +0.361 ns (all timing met) - 6,192 LUTs (4.6%), 9,064 FFs (3.4%), 16 BRAM (4.4%), 139 DSP48E1 (18.8%) - Total power: 0.732 W - Barrel-shift twiddle freed 1 DSP (140 -> 139) as expected - TCL script fix: wrap check_timing in catch (Vivado 2025.2 bug) - Updated release-notes.html, implementation-log.html, reports.html
493 lines
19 KiB
Tcl
493 lines
19 KiB
Tcl
################################################################################
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# build21_fft_e2e.tcl
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#
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# AERIS-10 Build 21: FFT Optimizations + E2E RTL Fixes
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# Target: XC7A200T-2FBG484I
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# Design: radar_system_top
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# Base: Build 20 (v0.1.3-build20, WNS +0.426 ns)
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#
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# Changes vs Build 20:
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# - fft_engine.v: merged SHIFT state into WRITE (5→4 cycle butterfly,
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# 20% throughput gain). Twiddle index uses barrel-shift instead of
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# multiplier (frees 1 DSP48).
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# - plfm_chirp_controller.v: TX/RX mixer enables now mutually exclusive
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# by FSM state (Fix #4).
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# - usb_data_interface.v: stream control reset default 3'b001 (range-only),
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# doppler/cfar data_pending sticky flags, write FSM triggers on
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# range_valid only (Fix #5).
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# - radar_receiver_final.v: STM32 toggle signal inputs for mode-00,
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# dynamic frame detection via host_chirps_per_elev.
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# - radar_system_top.v: STM32 toggle wiring to receiver instance.
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# - chirp_memory_loader_param.v: explicit readmemh range for short chirp.
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#
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# Expected impact:
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# - DSP48E1: 140 → 139 (−1 from barrel-shift twiddle, +0 net from
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# FFT multiplier removal; CIC CREG DSPs unchanged)
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# - LUT/FF: slight increase from USB data_pending logic + receiver
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# toggle inputs. Slight decrease from FFT state removal.
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# - Timing: should remain positive (Build 20 had +0.426 ns WNS).
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# Gap 2 build (pre-FFT-opt) had +0.078 ns WNS with similar RTL.
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#
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# Generates ALL reports required for the 15-point Vivado TCL Build Report.
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#
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# Usage:
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# vivado -mode batch -source build21_fft_e2e.tcl \
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# -log ~/PLFM_RADAR_work/vivado_project/build21.log \
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# -journal ~/PLFM_RADAR_work/vivado_project/build21.jou
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#
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# Author: auto-generated for Jason Stone
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# Date: 2026-03-20
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################################################################################
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# ==============================================================================
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# 0. Configuration
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# ==============================================================================
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set project_name "aeris10_radar"
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set project_dir "/home/jason-stone/PLFM_RADAR_work/vivado_project"
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set rtl_dir "/home/jason-stone/PLFM_RADAR_work/PLFM_RADAR/9_Firmware/9_2_FPGA"
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set top_module "radar_system_top"
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set fpga_part "xc7a200tfbg484-2"
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set report_dir "${project_dir}/reports_build21"
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set sim_dir "${project_dir}/sim"
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set bitstream_dir "${project_dir}/bitstream"
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set build_tag "build21"
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file mkdir $report_dir
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file mkdir $sim_dir
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file mkdir $bitstream_dir
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# Record start time
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set build_start [clock seconds]
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set build_timestamp [clock format $build_start -format {%Y-%m-%d %H:%M:%S}]
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puts "================================================================"
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puts " AERIS-10 Build 21: FFT Optimizations + E2E RTL Fixes"
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puts " Target: $fpga_part"
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puts " Top: $top_module"
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puts " Reports: $report_dir"
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puts " Started: $build_timestamp"
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puts "================================================================"
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# ==============================================================================
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# 1. Project Creation + Source Files
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# ==============================================================================
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create_project $project_name $project_dir -part $fpga_part -force
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set_property target_language Verilog [current_project]
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# --- Add RTL sources ---
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set rtl_files [list \
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"${rtl_dir}/adc_clk_mmcm.v" \
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"${rtl_dir}/ad9484_interface_400m.v" \
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"${rtl_dir}/cdc_modules.v" \
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"${rtl_dir}/chirp_lut_init.v" \
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"${rtl_dir}/chirp_memory_loader_param.v" \
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"${rtl_dir}/cic_decimator_4x_enhanced.v" \
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"${rtl_dir}/dac_interface_single.v" \
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"${rtl_dir}/ddc_400m.v" \
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"${rtl_dir}/ddc_input_interface.v" \
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"${rtl_dir}/doppler_processor.v" \
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"${rtl_dir}/edge_detector.v" \
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"${rtl_dir}/fft_1024_forward.v" \
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"${rtl_dir}/fft_1024_inverse.v" \
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"${rtl_dir}/fir_lowpass.v" \
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"${rtl_dir}/frequency_matched_filter.v" \
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"${rtl_dir}/latency_buffer.v" \
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"${rtl_dir}/level_shifter_interface.v" \
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"${rtl_dir}/lvds_to_cmos_400m.v" \
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"${rtl_dir}/matched_filter_multi_segment.v" \
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"${rtl_dir}/matched_filter_processing_chain.v" \
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"${rtl_dir}/nco_400m_enhanced.v" \
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"${rtl_dir}/plfm_chirp_controller.v" \
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"${rtl_dir}/radar_mode_controller.v" \
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"${rtl_dir}/radar_receiver_final.v" \
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"${rtl_dir}/radar_system_top.v" \
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"${rtl_dir}/radar_transmitter.v" \
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"${rtl_dir}/range_bin_decimator.v" \
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"${rtl_dir}/usb_data_interface.v" \
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"${rtl_dir}/usb_packet_analyzer.v" \
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"${rtl_dir}/xfft_32.v" \
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"${rtl_dir}/fft_engine.v" \
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]
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set file_count 0
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foreach f $rtl_files {
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if {[file exists $f]} {
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add_files -norecurse $f
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incr file_count
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} else {
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puts " WARNING: RTL file not found: $f"
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}
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}
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puts " Added $file_count RTL files"
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# Add .mem files for BRAM initialization
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set mem_files [glob -nocomplain "${rtl_dir}/*.mem"]
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foreach f $mem_files {
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add_files -norecurse $f
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puts " Added MEM: [file tail $f]"
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}
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# Add constraints — main production XDC + MMCM supplementary XDC (FIXED)
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add_files -fileset constrs_1 -norecurse "${project_dir}/synth_only.xdc"
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add_files -fileset constrs_1 -norecurse "${rtl_dir}/constraints/adc_clk_mmcm.xdc"
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set_property top $top_module [current_fileset]
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set_property verilog_define {FFT_XPM_BRAM} [current_fileset]
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# ==============================================================================
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# 2. Synthesis
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# ==============================================================================
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puts ""
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puts "================================================================"
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puts " Phase 1/5: Synthesis"
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puts "================================================================"
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set_property STEPS.SYNTH_DESIGN.ARGS.FLATTEN_HIERARCHY rebuilt [get_runs synth_1]
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set_property STEPS.SYNTH_DESIGN.ARGS.KEEP_EQUIVALENT_REGISTERS true [get_runs synth_1]
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set synth_start [clock seconds]
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launch_runs synth_1 -jobs 8
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wait_on_run synth_1
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set synth_elapsed [expr {[clock seconds] - $synth_start}]
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set synth_status [get_property STATUS [get_runs synth_1]]
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puts " Synthesis status: $synth_status"
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puts " Synthesis time: ${synth_elapsed}s ([expr {$synth_elapsed/60}]m [expr {$synth_elapsed%60}]s)"
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if {[string match "*ERROR*" $synth_status] || [string match "*FAILED*" $synth_status]} {
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puts "CRITICAL: SYNTHESIS FAILED — aborting build"
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close_project
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exit 1
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}
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# Post-synth timing (for comparison)
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open_run synth_1 -name synth_1
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report_timing_summary -delay_type min_max -max_paths 10 -file "${report_dir}/01_timing_post_synth.rpt"
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report_utilization -file "${report_dir}/01_utilization_post_synth.rpt"
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close_design
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# ==============================================================================
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# 3. Implementation (opt → place → phys_opt → route → post_route_phys_opt)
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# ==============================================================================
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puts ""
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puts "================================================================"
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puts " Phase 2/5: Implementation"
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puts "================================================================"
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# Aggressive directives for best timing
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set_property STEPS.OPT_DESIGN.ARGS.DIRECTIVE Explore [get_runs impl_1]
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set_property STEPS.PLACE_DESIGN.ARGS.DIRECTIVE ExtraTimingOpt [get_runs impl_1]
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set_property STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE AggressiveExplore [get_runs impl_1]
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set_property STEPS.PHYS_OPT_DESIGN.IS_ENABLED true [get_runs impl_1]
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set_property STEPS.ROUTE_DESIGN.ARGS.DIRECTIVE AggressiveExplore [get_runs impl_1]
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set_property STEPS.POST_ROUTE_PHYS_OPT_DESIGN.IS_ENABLED true [get_runs impl_1]
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set_property STEPS.POST_ROUTE_PHYS_OPT_DESIGN.ARGS.DIRECTIVE AggressiveExplore [get_runs impl_1]
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set impl_start [clock seconds]
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launch_runs impl_1 -jobs 8
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wait_on_run impl_1
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set impl_elapsed [expr {[clock seconds] - $impl_start}]
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set impl_status [get_property STATUS [get_runs impl_1]]
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puts " Implementation status: $impl_status"
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puts " Implementation time: ${impl_elapsed}s ([expr {$impl_elapsed/60}]m [expr {$impl_elapsed%60}]s)"
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if {![string match "*Complete*" $impl_status]} {
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puts "CRITICAL: IMPLEMENTATION FAILED: $impl_status"
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close_project
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exit 1
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}
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# ==============================================================================
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# 4. Bitstream Generation
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# ==============================================================================
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puts ""
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puts "================================================================"
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puts " Phase 3/5: Bitstream Generation"
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puts "================================================================"
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set bit_start [clock seconds]
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launch_runs impl_1 -to_step write_bitstream -jobs 8
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wait_on_run impl_1
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set bit_elapsed [expr {[clock seconds] - $bit_start}]
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puts " Bitstream time: ${bit_elapsed}s"
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# Copy bitstream to known location
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set bit_src "${project_dir}/aeris10_radar.runs/impl_1/${top_module}.bit"
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if {[file exists $bit_src]} {
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file copy -force $bit_src "${bitstream_dir}/${top_module}_${build_tag}.bit"
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puts " Bitstream: ${bitstream_dir}/${top_module}_${build_tag}.bit"
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puts " Size: [file size $bit_src] bytes"
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} else {
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puts " WARNING: Bitstream file not found at $bit_src"
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}
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# ==============================================================================
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# 5. Comprehensive Report Generation
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# ==============================================================================
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puts ""
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puts "================================================================"
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puts " Phase 4/5: Report Generation (15-point checklist)"
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puts "================================================================"
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# Open the routed design for reporting
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open_run impl_1 -name impl_1
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# --- Checklist Item 2: Timing Summary ---
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puts " [2/15] Timing Summary..."
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report_timing_summary -delay_type min_max -max_paths 100 \
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-report_unconstrained \
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-file "${report_dir}/02_timing_summary.rpt"
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# --- Checklist Item 3: Clock Analysis ---
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puts " [3/15] Clock Analysis..."
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report_clocks -file "${report_dir}/03_clocks.rpt"
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report_clock_interaction -delay_type min_max \
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-file "${report_dir}/03_clock_interaction.rpt"
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report_clock_networks -file "${report_dir}/03_clock_networks.rpt"
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# --- Checklist Item 4: Utilization ---
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puts " [4/15] Utilization..."
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report_utilization -file "${report_dir}/04_utilization.rpt"
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report_utilization -hierarchical -file "${report_dir}/04_utilization_hierarchical.rpt"
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# --- Checklist Item 5: Power ---
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puts " [5/15] Power Report..."
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report_power -file "${report_dir}/05_power.rpt"
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# --- Checklist Item 6: DRC ---
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puts " [6/15] DRC..."
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report_drc -file "${report_dir}/06_drc.rpt"
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# --- Checklist Item 7: IO and Constraints ---
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puts " [7/15] IO Report..."
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report_io -file "${report_dir}/07_io.rpt"
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report_timing -from [all_inputs] -to [all_outputs] -max_paths 20 \
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-file "${report_dir}/07_io_timing.rpt"
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# --- Checklist Item 8: Congestion Analysis ---
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puts " [8/15] Congestion Analysis..."
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report_design_analysis -congestion -file "${report_dir}/08_congestion.rpt"
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# --- Checklist Item 9: Route Status ---
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puts " [9/15] Route Status..."
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report_route_status -file "${report_dir}/09_route_status.rpt"
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# --- Checklist Item 10: Critical Paths ---
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puts " [10/15] Critical Paths..."
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report_timing -max_paths 20 -sort_by slack -nworst 5 \
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-file "${report_dir}/10_critical_paths_setup.rpt"
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report_timing -delay_type min -max_paths 20 -sort_by slack -nworst 5 \
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-file "${report_dir}/10_critical_paths_hold.rpt"
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report_high_fanout_nets -timing -load_type -max_nets 20 \
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-file "${report_dir}/10_high_fanout_nets.rpt"
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# --- Checklist Item 11: QoR Summary ---
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puts " [11/15] QoR Summary..."
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report_design_analysis -timing -file "${report_dir}/11_design_analysis_timing.rpt"
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report_design_analysis -logic_level_distribution -file "${report_dir}/11_logic_level_dist.rpt"
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report_methodology -file "${report_dir}/11_methodology.rpt"
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# --- Checklist Item 12: CDC Analysis ---
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puts " [12/15] CDC Analysis..."
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report_cdc -details -file "${report_dir}/12_cdc.rpt"
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# --- Checklist Item 13: Log Scan (captured separately in build log) ---
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puts " [13/15] Log scan — see build21.log"
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# --- Additional reports ---
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puts " [extra] Generating additional diagnostic reports..."
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# report_exceptions can fail in Vivado 2025.2 — wrap in catch
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if {[catch {report_exceptions -file "${report_dir}/13_exceptions.rpt"} err]} {
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puts " WARNING: report_exceptions failed: $err"
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puts " (Known Vivado 2025.2 issue — non-critical)"
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}
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if {[catch {check_timing -verbose -file "${report_dir}/13_check_timing.rpt"} err]} {
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puts " WARNING: check_timing failed: $err"
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puts " (Known Vivado 2025.2 issue — non-critical)"
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}
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# Compile configuration summary into a single text file
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set summary_fh [open "${report_dir}/00_build21_summary.txt" w]
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puts $summary_fh "================================================================"
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puts $summary_fh " AERIS-10 Build 21 — FFT Optimizations + E2E RTL Fixes"
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puts $summary_fh "================================================================"
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puts $summary_fh ""
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puts $summary_fh "Build Tag: $build_tag"
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puts $summary_fh "Build Timestamp: $build_timestamp"
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puts $summary_fh "FPGA Part: $fpga_part"
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puts $summary_fh "Top Module: $top_module"
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puts $summary_fh "RTL Files: $file_count"
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puts $summary_fh "Synth Status: $synth_status"
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puts $summary_fh "Synth Time: ${synth_elapsed}s"
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puts $summary_fh "Impl Status: $impl_status"
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puts $summary_fh "Impl Time: ${impl_elapsed}s"
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puts $summary_fh "Bitstream Time: ${bit_elapsed}s"
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puts $summary_fh ""
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# Extract key timing numbers
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puts $summary_fh "--- Timing ---"
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set wns [get_property STATS.WNS [current_design]]
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set tns [get_property STATS.TNS [current_design]]
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set whs [get_property STATS.WHS [current_design]]
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set ths [get_property STATS.THS [current_design]]
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set fail_ep [get_property STATS.TPWS [current_design]]
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puts $summary_fh " WNS: $wns ns"
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puts $summary_fh " TNS: $tns ns"
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puts $summary_fh " WHS: $whs ns"
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puts $summary_fh " THS: $ths ns"
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puts $summary_fh ""
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puts $summary_fh " Build 20 Baseline: WNS = +0.426 ns, WHS = +0.058 ns"
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puts $summary_fh " Gap 2 Build (ref): WNS = +0.078 ns, WHS = +0.054 ns"
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puts $summary_fh " Delta WNS vs B20: [expr {$wns - 0.426}] ns"
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puts $summary_fh " Delta WHS vs B20: [expr {$whs - 0.058}] ns"
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puts $summary_fh ""
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# Extract utilization
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puts $summary_fh "--- Utilization ---"
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set lut_used [llength [get_cells -hierarchical -filter {PRIMITIVE_TYPE =~ CLB.LUT.*}]]
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set ff_used [llength [get_cells -hierarchical -filter {PRIMITIVE_TYPE =~ CLB.FF.*}]]
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set bram_used [llength [get_cells -hierarchical -filter {PRIMITIVE_TYPE =~ BMEM.*}]]
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set dsp_used [llength [get_cells -hierarchical -filter {PRIMITIVE_TYPE =~ MULT.DSP.*}]]
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puts $summary_fh " LUTs: $lut_used / 134600"
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puts $summary_fh " FFs: $ff_used / 269200"
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puts $summary_fh " BRAM: $bram_used cells"
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puts $summary_fh " DSP: $dsp_used cells"
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puts $summary_fh ""
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puts $summary_fh " Build 20 Baseline: LUTs=6092, FFs=9024, BRAM=16, DSP=140"
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puts $summary_fh " Gap 2 Build (ref): LUTs=6343, FFs=9197, BRAM=16, DSP=140"
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puts $summary_fh " Expected Build 21: DSP ~139 (−1 from barrel-shift twiddle)"
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puts $summary_fh ""
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# Route status
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set unrouted [llength [get_nets -hierarchical -filter {ROUTE_STATUS == UNROUTED}]]
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puts $summary_fh "--- Route ---"
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puts $summary_fh " Unrouted nets: $unrouted"
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puts $summary_fh ""
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# MMCM usage
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puts $summary_fh "--- MMCM Usage (Gap 7) ---"
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set mmcm_count [llength [get_cells -hierarchical -filter {PRIMITIVE_TYPE =~ CLOCK.MMCM.*}]]
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puts $summary_fh " MMCME2 used: $mmcm_count / 10"
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puts $summary_fh " Expected: 1 (adc_clk_mmcm jitter cleaner)"
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puts $summary_fh ""
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# Bitstream
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if {[file exists $bit_src]} {
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puts $summary_fh "--- Bitstream ---"
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puts $summary_fh " File: ${top_module}_${build_tag}.bit"
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puts $summary_fh " Size: [file size $bit_src] bytes"
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} else {
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puts $summary_fh "--- Bitstream ---"
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puts $summary_fh " WARNING: NOT GENERATED"
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}
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puts $summary_fh ""
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# Signoff
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puts $summary_fh "--- Final Signoff ---"
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set signoff_pass 1
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if {$wns < 0} {
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puts $summary_fh " FAIL: WNS = $wns (negative slack)"
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set signoff_pass 0
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} else {
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puts $summary_fh " PASS: WNS = $wns ns (no setup violations)"
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}
|
||
if {$whs < 0} {
|
||
puts $summary_fh " FAIL: WHS = $whs (hold violation)"
|
||
set signoff_pass 0
|
||
} else {
|
||
puts $summary_fh " PASS: WHS = $whs ns (no hold violations)"
|
||
}
|
||
if {$tns != 0} {
|
||
puts $summary_fh " FAIL: TNS = $tns (total negative slack)"
|
||
set signoff_pass 0
|
||
} else {
|
||
puts $summary_fh " PASS: TNS = 0 ns"
|
||
}
|
||
if {$unrouted > 0} {
|
||
puts $summary_fh " FAIL: $unrouted unrouted nets"
|
||
set signoff_pass 0
|
||
} else {
|
||
puts $summary_fh " PASS: All nets routed"
|
||
}
|
||
if {[file exists $bit_src]} {
|
||
puts $summary_fh " PASS: Bitstream generated"
|
||
} else {
|
||
puts $summary_fh " FAIL: No bitstream"
|
||
set signoff_pass 0
|
||
}
|
||
puts $summary_fh ""
|
||
|
||
# Timing regression check vs Build 20
|
||
if {$wns < 0.078} {
|
||
puts $summary_fh " *** WARNING: WNS REGRESSED below Gap 2 build (was +0.078 ns, now $wns ns) ***"
|
||
puts $summary_fh " *** Review critical paths — FFT opts or RTL fixes may have introduced new timing pressure ***"
|
||
}
|
||
if {$whs < 0.054} {
|
||
puts $summary_fh " *** WARNING: WHS REGRESSED below Gap 2 build (was +0.054 ns, now $whs ns) ***"
|
||
}
|
||
|
||
if {$signoff_pass} {
|
||
puts $summary_fh " *** SIGNOFF: PASS ***"
|
||
} else {
|
||
puts $summary_fh " *** SIGNOFF: FAIL ***"
|
||
}
|
||
|
||
close $summary_fh
|
||
puts " Summary written to: ${report_dir}/00_build21_summary.txt"
|
||
|
||
# ==============================================================================
|
||
# 6. SDF + Timing Netlist (for post-route simulation)
|
||
# ==============================================================================
|
||
|
||
puts ""
|
||
puts "================================================================"
|
||
puts " Phase 5/5: SDF + Timing Netlist"
|
||
puts "================================================================"
|
||
|
||
write_verilog -force -mode timesim "${sim_dir}/post_impl_timesim.v"
|
||
write_sdf -force "${sim_dir}/post_impl_timesim.sdf"
|
||
|
||
close_design
|
||
open_run synth_1 -name synth_1
|
||
write_verilog -force -mode funcsim "${sim_dir}/post_synth_funcsim.v"
|
||
|
||
# ==============================================================================
|
||
# Done
|
||
# ==============================================================================
|
||
|
||
set build_total [expr {[clock seconds] - $build_start}]
|
||
set build_end [clock format [clock seconds] -format {%Y-%m-%d %H:%M:%S}]
|
||
|
||
puts ""
|
||
puts "================================================================"
|
||
puts " BUILD 21 COMPLETE"
|
||
puts "================================================================"
|
||
puts " Started: $build_timestamp"
|
||
puts " Finished: $build_end"
|
||
puts " Total time: ${build_total}s ([expr {$build_total/60}]m [expr {$build_total%60}]s)"
|
||
puts " Synth: ${synth_elapsed}s"
|
||
puts " Impl: ${impl_elapsed}s"
|
||
puts " Bitstream: ${bit_elapsed}s"
|
||
puts " Reports: $report_dir"
|
||
puts " Bitstream: ${bitstream_dir}/${top_module}_${build_tag}.bit"
|
||
puts " WNS: $wns ns | WHS: $whs ns | TNS: $tns ns"
|
||
puts " Build 20 baseline: WNS +0.426 | WHS +0.058"
|
||
puts " Gap 2 build (ref): WNS +0.078 | WHS +0.054"
|
||
if {$signoff_pass} {
|
||
puts " SIGNOFF: PASS"
|
||
} else {
|
||
puts " SIGNOFF: FAIL"
|
||
}
|
||
puts "================================================================"
|
||
|
||
close_project
|
||
puts "Done."
|