00fbab6c9d
Complete FPGA timing closure across all clock domains after 9 iterative Vivado builds. WNS improved from -48.325ns to +0.018ns (107,886 endpoints). RTL fixes for 400 MHz timing: - NCO: 6-stage pipeline with DSP48E1 phase accumulator, registered LUT index (Fix D splits address decode from ROM read), distributed RAM - CIC: explicit DSP48E1 PCOUT->PCIN cascade for 5 integrator stages, CREG=1 on integrator_0 to eliminate fabric->DSP setup violation - DDC: 400 MHz reset synchronizer (async-assert/sync-deassert), active-high reset register for DSP48E1 RST ports, posedge output stage - FIR: 5-stage binary adder tree pipeline (7-cycle latency) - FFT: 5-cycle butterfly pipeline with registered twiddle index, XPM_MEMORY_TDPRAM for data storage - XDC: CDC false paths, async reset false paths, CIC comb multicycle paths Final Build 9 timing (all MET): adc_dco_p (400 MHz): WNS = +0.278ns clk_100m (100 MHz): WNS = +0.018ns clk_120m_dac (120 MHz): WNS = +0.992ns ft601_clk_in (100 MHz): WNS = +5.229ns Cross-domain (adc_dco_p->clk_100m): WNS = +7.105ns
342 lines
15 KiB
Verilog
342 lines
15 KiB
Verilog
`timescale 1ns / 1ps
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module tb_nco_400m;
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// ── Parameters ─────────────────────────────────────────────
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localparam CLK_PERIOD = 2.5; // 400 MHz
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// Frequency tuning words: f_out = FTW * f_clk / 2^32
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localparam [31:0] FTW_120MHZ = 32'h4CCCCCCD; // 120 MHz
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localparam [31:0] FTW_10MHZ = 32'h06666666; // 10 MHz
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localparam [31:0] FTW_1MHZ = 32'h00A3D70A; // 1 MHz
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// ── Signals ────────────────────────────────────────────────
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reg clk_400m;
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reg reset_n;
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reg [31:0] frequency_tuning_word;
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reg phase_valid;
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reg [15:0] phase_offset;
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wire signed [15:0] sin_out;
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wire signed [15:0] cos_out;
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wire dds_ready;
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// ── Test variables (all at module scope for Icarus) ────────
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integer pass_count;
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integer fail_count;
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integer test_num;
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integer csv_file;
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integer sample_count;
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reg signed [15:0] sin_max, sin_min, cos_max, cos_min;
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reg signed [15:0] sin_no_offset_3;
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reg signed [15:0] sin_offset_3;
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reg signed [15:0] sin_before_gate;
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reg [31:0] mag_sq;
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reg [31:0] mag_sq_min, mag_sq_max;
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// ── Clock ──────────────────────────────────────────────────
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always #(CLK_PERIOD/2) clk_400m = ~clk_400m;
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// ── DUT ────────────────────────────────────────────────────
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nco_400m_enhanced uut (
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.clk_400m (clk_400m),
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.reset_n (reset_n),
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.frequency_tuning_word(frequency_tuning_word),
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.phase_valid (phase_valid),
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.phase_offset (phase_offset),
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.sin_out (sin_out),
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.cos_out (cos_out),
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.dds_ready (dds_ready)
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);
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// ── Check task ─────────────────────────────────────────────
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task check;
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input cond;
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input [511:0] label;
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begin
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test_num = test_num + 1;
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if (cond) begin
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$display("[PASS] Test %0d: %0s", test_num, label);
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pass_count = pass_count + 1;
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end else begin
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$display("[FAIL] Test %0d: %0s", test_num, label);
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fail_count = fail_count + 1;
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end
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end
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endtask
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// ── Stimulus ───────────────────────────────────────────────
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initial begin
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$dumpfile("tb_nco_400m.vcd");
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$dumpvars(0, tb_nco_400m);
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// Init
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clk_400m = 0;
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reset_n = 0;
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frequency_tuning_word = 32'd0;
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phase_valid = 0;
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phase_offset = 16'd0;
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pass_count = 0;
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fail_count = 0;
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test_num = 0;
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// ════════════════════════════════════════════════════════
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// TEST GROUP 1: Reset behaviour
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// ════════════════════════════════════════════════════════
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$display("\n--- Test Group 1: Reset Behaviour ---");
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repeat (4) @(posedge clk_400m);
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#1;
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check(sin_out === 16'h0000, "sin_out = 0 during reset");
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check(cos_out === 16'h7FFF, "cos_out = 0x7FFF during reset");
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check(dds_ready === 1'b0, "dds_ready = 0 during reset");
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// Release reset
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reset_n = 1;
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@(posedge clk_400m); #1;
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check(dds_ready === 1'b0, "dds_ready stays 0 with phase_valid=0");
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// ════════════════════════════════════════════════════════
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// TEST GROUP 2: Basic operation at 1 MHz
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// ════════════════════════════════════════════════════════
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$display("\n--- Test Group 2: 1 MHz NCO Operation ---");
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frequency_tuning_word = FTW_1MHZ;
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phase_valid = 1;
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sin_max = -16'sh7FFF;
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sin_min = 16'sh7FFF;
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cos_max = -16'sh7FFF;
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cos_min = 16'sh7FFF;
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csv_file = $fopen("nco_1mhz_output.csv", "w");
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$fwrite(csv_file, "sample,sin_out,cos_out,dds_ready\n");
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for (sample_count = 0; sample_count < 500; sample_count = sample_count + 1) begin
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@(posedge clk_400m); #1;
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$fwrite(csv_file, "%0d,%0d,%0d,%0d\n",
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sample_count, sin_out, cos_out, dds_ready);
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if (dds_ready) begin
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if (sin_out > sin_max) sin_max = sin_out;
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if (sin_out < sin_min) sin_min = sin_out;
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if (cos_out > cos_max) cos_max = cos_out;
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if (cos_out < cos_min) cos_min = cos_out;
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end
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end
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$fclose(csv_file);
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$display(" 1 MHz: sin range [%0d, %0d], cos range [%0d, %0d]",
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sin_min, sin_max, cos_min, cos_max);
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check(sin_max > 16'sh1000, "sin has positive amplitude > 0x1000");
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check(sin_min < -16'sh1000, "sin has negative amplitude");
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check(cos_max > 16'sh1000, "cos has positive amplitude > 0x1000");
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check(cos_min < -16'sh1000, "cos has negative amplitude");
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check(dds_ready === 1'b1, "dds_ready asserted during operation");
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// ════════════════════════════════════════════════════════
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// TEST GROUP 3: 120 MHz IF (primary operating frequency)
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// ════════════════════════════════════════════════════════
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$display("\n--- Test Group 3: 120 MHz NCO Operation ---");
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reset_n = 0;
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phase_valid = 0;
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repeat (4) @(posedge clk_400m);
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reset_n = 1;
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@(posedge clk_400m);
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frequency_tuning_word = FTW_120MHZ;
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phase_valid = 1;
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sin_max = -16'sh7FFF;
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sin_min = 16'sh7FFF;
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cos_max = -16'sh7FFF;
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cos_min = 16'sh7FFF;
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csv_file = $fopen("nco_120mhz_output.csv", "w");
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$fwrite(csv_file, "sample,sin_out,cos_out,dds_ready\n");
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for (sample_count = 0; sample_count < 100; sample_count = sample_count + 1) begin
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@(posedge clk_400m); #1;
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$fwrite(csv_file, "%0d,%0d,%0d,%0d\n",
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sample_count, sin_out, cos_out, dds_ready);
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if (dds_ready) begin
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if (sin_out > sin_max) sin_max = sin_out;
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if (sin_out < sin_min) sin_min = sin_out;
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if (cos_out > cos_max) cos_max = cos_out;
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if (cos_out < cos_min) cos_min = cos_out;
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end
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end
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$fclose(csv_file);
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$display(" 120 MHz: sin range [%0d, %0d], cos range [%0d, %0d]",
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sin_min, sin_max, cos_min, cos_max);
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check(sin_max > 16'sh1000, "120MHz sin positive swing");
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check(sin_min < -16'sh1000, "120MHz sin negative swing");
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check(cos_max > 16'sh1000, "120MHz cos positive swing");
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check(cos_min < -16'sh1000, "120MHz cos negative swing");
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// ════════════════════════════════════════════════════════
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// TEST GROUP 4: Phase offset
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// ════════════════════════════════════════════════════════
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$display("\n--- Test Group 4: Phase Offset ---");
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// Use 10 MHz so phase accumulates fast enough for offset to matter
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reset_n = 0;
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phase_valid = 0;
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repeat (4) @(posedge clk_400m);
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reset_n = 1;
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@(posedge clk_400m);
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frequency_tuning_word = FTW_10MHZ;
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phase_offset = 16'h0000;
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phase_valid = 1;
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// Let NCO run long enough for phase to reach a non-trivial region
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repeat (20) @(posedge clk_400m);
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#1; sin_no_offset_3 = sin_out;
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// Reset and apply 90-degree phase offset
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reset_n = 0;
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phase_valid = 0;
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repeat (4) @(posedge clk_400m);
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reset_n = 1;
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@(posedge clk_400m);
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frequency_tuning_word = FTW_10MHZ;
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phase_offset = 16'h4000; // 90 degrees
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phase_valid = 1;
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repeat (20) @(posedge clk_400m);
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#1; sin_offset_3 = sin_out;
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$display(" sin(no_offset, t=20) = %0d, sin(+90deg, t=20) = %0d",
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sin_no_offset_3, sin_offset_3);
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check(sin_no_offset_3 !== sin_offset_3,
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"Phase offset changes sin output");
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// ════════════════════════════════════════════════════════
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// TEST GROUP 5: Dynamic frequency change
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// ════════════════════════════════════════════════════════
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$display("\n--- Test Group 5: Dynamic Frequency Change ---");
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reset_n = 0;
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phase_valid = 0;
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phase_offset = 16'h0000;
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repeat (4) @(posedge clk_400m);
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reset_n = 1;
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@(posedge clk_400m);
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frequency_tuning_word = FTW_1MHZ;
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phase_valid = 1;
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repeat (50) @(posedge clk_400m);
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// Switch to 10 MHz mid-stream
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frequency_tuning_word = FTW_10MHZ;
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csv_file = $fopen("nco_freq_switch.csv", "w");
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$fwrite(csv_file, "sample,sin_out,cos_out\n");
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for (sample_count = 0; sample_count < 200; sample_count = sample_count + 1) begin
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@(posedge clk_400m); #1;
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$fwrite(csv_file, "%0d,%0d,%0d\n",
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sample_count, sin_out, cos_out);
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end
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$fclose(csv_file);
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check(1'b1, "Frequency switch completed without error");
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// ════════════════════════════════════════════════════════
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// TEST GROUP 6: phase_valid gating
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// ════════════════════════════════════════════════════════
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$display("\n--- Test Group 6: phase_valid Gating ---");
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reset_n = 0;
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phase_valid = 0;
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phase_offset = 16'h0000;
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repeat (4) @(posedge clk_400m);
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reset_n = 1;
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@(posedge clk_400m);
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frequency_tuning_word = FTW_10MHZ;
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phase_valid = 1;
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repeat (10) @(posedge clk_400m);
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#1;
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sin_before_gate = sin_out;
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// Deassert phase_valid — with 6-stage pipeline, dds_ready has 7-cycle latency
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phase_valid = 0;
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repeat (8) @(posedge clk_400m); #1;
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check(dds_ready === 1'b0, "dds_ready deasserts when phase_valid=0");
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repeat (10) @(posedge clk_400m);
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// Re-enable — wait for pipeline to refill (7 cycles)
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phase_valid = 1;
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repeat (8) @(posedge clk_400m); #1;
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check(dds_ready === 1'b1, "dds_ready re-asserts when phase_valid=1");
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// ════════════════════════════════════════════════════════
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// TEST GROUP 7: Quadrature orthogonality (sin^2+cos^2)
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// ════════════════════════════════════════════════════════
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$display("\n--- Test Group 7: Quadrature Orthogonality ---");
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reset_n = 0;
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phase_valid = 0;
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phase_offset = 16'h0000;
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repeat (4) @(posedge clk_400m);
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reset_n = 1;
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@(posedge clk_400m);
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frequency_tuning_word = FTW_10MHZ;
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phase_valid = 1;
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// Skip pipeline warmup (6-stage pipeline + 1 for dds_ready)
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repeat (7) @(posedge clk_400m);
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mag_sq_min = 32'hFFFFFFFF;
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mag_sq_max = 32'h00000000;
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csv_file = $fopen("nco_quadrature.csv", "w");
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$fwrite(csv_file, "sample,sin,cos,mag_sq\n");
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for (sample_count = 0; sample_count < 40; sample_count = sample_count + 1) begin
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@(posedge clk_400m); #1;
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if (dds_ready) begin
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mag_sq = (sin_out * sin_out) + (cos_out * cos_out);
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if (mag_sq < mag_sq_min) mag_sq_min = mag_sq;
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if (mag_sq > mag_sq_max) mag_sq_max = mag_sq;
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$fwrite(csv_file, "%0d,%0d,%0d,%0d\n",
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sample_count, sin_out, cos_out, mag_sq);
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end
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end
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$fclose(csv_file);
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$display(" |sin|^2+|cos|^2: min=%0d, max=%0d, ratio=%.2f",
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mag_sq_min, mag_sq_max,
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1.0 * mag_sq_max / (mag_sq_min > 0 ? mag_sq_min : 1));
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// With corrected quarter-wave sine LUT, sin^2+cos^2 should be
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// nearly constant (ratio ~1.02x). Using 2x threshold to avoid
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// 32-bit overflow in the multiply (min*5 overflowed before).
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check(mag_sq_max > 0, "Magnitude squared is non-zero");
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check(mag_sq_min > 0, "Magnitude squared minimum > 0");
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// Strict check: with correct LUT, variance should be < 1.1x
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// Use division to avoid 32-bit overflow: max/min < 2
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check(mag_sq_max < (mag_sq_min * 2), "Quadrature magnitude variance < 2x (near-ideal)");
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// ════════════════════════════════════════════════════════
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// Summary
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// ════════════════════════════════════════════════════════
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$display("");
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$display("========================================");
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$display(" NCO 400M TESTBENCH RESULTS");
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$display(" PASSED: %0d / %0d", pass_count, test_num);
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$display(" FAILED: %0d / %0d", fail_count, test_num);
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if (fail_count == 0)
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$display(" ** ALL TESTS PASSED **");
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else
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$display(" ** SOME TESTS FAILED **");
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$display("========================================");
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$display("");
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#100;
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$finish;
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end
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endmodule
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