46 lines
1.3 KiB
Verilog
46 lines
1.3 KiB
Verilog
`timescale 1ns / 1ps
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module lvds_to_cmos_400m (
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// ADC Physical Interface (LVDS Inputs)
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input wire clk_400m_p, // Data Clock Output P (400MHz LVDS, 2.5V)
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input wire clk_400m_n, // Data Clock Output N (400MHz LVDS, 2.5V)
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input wire reset_n, // Active-low reset
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// CMOS Output Interface (400MHz Domain)
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output reg clk_400m_cmos // ADC data clock (CMOS, 3.3V)
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);
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// LVDS to single-ended conversion
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wire clk_400m_se; // Single-ended DCO from ADC
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// IBUFDS for DCO clock (LVDS to CMOS conversion)
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IBUFDS #(
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.DIFF_TERM("FALSE"), // DISABLE internal termination (using external 100O)
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.IOSTANDARD("LVDS_25") // 2.5V LVDS standard
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) ibufds_dco (
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.O(clk_400m_se), // Single-ended 400MHz clock
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.I(clk_400m_p),
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.IB(clk_400m_n)
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);
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// Optional: Global clock buffer for better clock distribution
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wire clk_400m_buffered;
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BUFG bufg_dco (
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.I(clk_400m_se),
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.O(clk_400m_buffered)
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);
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// Main processing: Capture on rising edge only
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always @(posedge clk_400m_buffered or negedge reset_n) begin
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if (!reset_n) begin
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// Reset state
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clk_400m_cmos <= 1'b0;
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end else begin
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// Output buffered DCO clock
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clk_400m_cmos <= clk_400m_buffered;
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end
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end
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endmodule
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