Files
overwatch/9_Firmware/9_2_FPGA/tb/mf_pipeline_output.csv
Jason 558f49cd4a Add 8 Verilog testbenches with full coverage (144/144 pass)
Testbenches for: edge_detector (17), nco_400m (20), cic_decimator (14),
fir_lowpass (13), freq_matched_filter (14), ddc_400m full-chain (7),
chirp_controller (39), chirp_contract regression (20).

Includes CSV output data for waveform verification.
Add .gitignore to exclude VCD/VVP build artifacts.
2026-03-15 06:14:11 +02:00

1.2 KiB

1samplefft_realfft_imagref_realref_imagout_realout_imagvalid
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