558f49cd4a
Testbenches for: edge_detector (17), nco_400m (20), cic_decimator (14), fir_lowpass (13), freq_matched_filter (14), ddc_400m full-chain (7), chirp_controller (39), chirp_contract regression (20). Includes CSV output data for waveform verification. Add .gitignore to exclude VCD/VVP build artifacts.
247 lines
11 KiB
Verilog
247 lines
11 KiB
Verilog
`timescale 1ns / 1ps
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module tb_ddc_400m;
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// ── Clock parameters ───────────────────────────────────────
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localparam CLK_400M_PERIOD = 2.5; // 400 MHz
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localparam CLK_100M_PERIOD = 10.0; // 100 MHz
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// ── Signals ────────────────────────────────────────────────
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reg clk_400m;
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reg clk_100m;
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reg reset_n;
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reg mixers_enable;
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reg [7:0] adc_data;
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reg adc_data_valid_i;
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reg adc_data_valid_q;
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wire signed [17:0] baseband_i;
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wire signed [17:0] baseband_q;
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wire baseband_valid_i;
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wire baseband_valid_q;
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wire [1:0] ddc_status;
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wire [7:0] ddc_diagnostics;
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wire mixer_saturation;
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wire filter_overflow;
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reg bypass_mode;
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reg [1:0] test_mode;
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reg [15:0] test_phase_inc;
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reg force_saturation;
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reg reset_monitors;
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wire [31:0] debug_sample_count;
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wire [17:0] debug_internal_i;
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wire [17:0] debug_internal_q;
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// ── Test variables ─────────────────────────────────────────
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integer pass_count;
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integer fail_count;
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integer test_num;
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integer csv_file;
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integer sample_count;
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integer output_count;
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reg signed [17:0] bb_i_max, bb_i_min, bb_q_max, bb_q_min;
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// ── Clocks ─────────────────────────────────────────────────
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always #(CLK_400M_PERIOD/2) clk_400m = ~clk_400m;
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always #(CLK_100M_PERIOD/2) clk_100m = ~clk_100m;
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// ── DUT ────────────────────────────────────────────────────
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ddc_400m_enhanced uut (
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.clk_400m (clk_400m),
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.clk_100m (clk_100m),
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.reset_n (reset_n),
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.mixers_enable (mixers_enable),
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.adc_data (adc_data),
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.adc_data_valid_i (adc_data_valid_i),
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.adc_data_valid_q (adc_data_valid_q),
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.baseband_i (baseband_i),
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.baseband_q (baseband_q),
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.baseband_valid_i (baseband_valid_i),
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.baseband_valid_q (baseband_valid_q),
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.ddc_status (ddc_status),
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.ddc_diagnostics (ddc_diagnostics),
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.mixer_saturation (mixer_saturation),
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.filter_overflow (filter_overflow),
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.bypass_mode (bypass_mode),
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.test_mode (test_mode),
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.test_phase_inc (test_phase_inc),
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.force_saturation (force_saturation),
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.reset_monitors (reset_monitors),
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.debug_sample_count(debug_sample_count),
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.debug_internal_i (debug_internal_i),
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.debug_internal_q (debug_internal_q)
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);
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// ── Check task ─────────────────────────────────────────────
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task check;
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input cond;
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input [511:0] label;
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begin
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test_num = test_num + 1;
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if (cond) begin
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$display("[PASS] Test %0d: %0s", test_num, label);
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pass_count = pass_count + 1;
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end else begin
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$display("[FAIL] Test %0d: %0s", test_num, label);
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fail_count = fail_count + 1;
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end
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end
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endtask
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// ── Stimulus ───────────────────────────────────────────────
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initial begin
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$dumpfile("tb_ddc_400m.vcd");
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$dumpvars(0, tb_ddc_400m);
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// Init
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clk_400m = 0;
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clk_100m = 0;
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reset_n = 0;
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mixers_enable = 0;
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adc_data = 0;
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adc_data_valid_i = 0;
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adc_data_valid_q = 0;
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bypass_mode = 0;
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test_mode = 2'b00;
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test_phase_inc = 0;
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force_saturation = 0;
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reset_monitors = 0;
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pass_count = 0;
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fail_count = 0;
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test_num = 0;
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// ════════════════════════════════════════════════════════
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// TEST GROUP 1: Reset behaviour
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// ════════════════════════════════════════════════════════
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$display("\n--- Test Group 1: Reset Behaviour ---");
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repeat (10) @(posedge clk_400m);
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#1;
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check(baseband_i === 18'sd0, "baseband_i = 0 during reset");
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check(baseband_q === 18'sd0, "baseband_q = 0 during reset");
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check(baseband_valid_i === 1'b0, "baseband_valid_i = 0 during reset");
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// Release reset
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reset_n = 1;
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repeat (10) @(posedge clk_400m);
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#1;
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// ════════════════════════════════════════════════════════
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// TEST GROUP 2: Full DDC chain with 120 MHz IF tone
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// ════════════════════════════════════════════════════════
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$display("\n--- Test Group 2: 120 MHz IF Tone Through DDC ---");
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// Generate a 120 MHz sinusoid as 8-bit ADC data
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// At 400 MSPS: sin(2*pi*120e6/400e6 * n) = sin(0.6*pi*n)
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// 8-bit unsigned: mid=128, amplitude=100
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mixers_enable = 1;
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adc_data_valid_i = 1;
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adc_data_valid_q = 1;
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csv_file = $fopen("ddc_120mhz_output.csv", "w");
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$fwrite(csv_file, "input_n,adc_data,bb_i,bb_q,bb_valid_i\n");
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output_count = 0;
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bb_i_max = -18'sh1FFFF;
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bb_i_min = 18'sh1FFFF;
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bb_q_max = -18'sh1FFFF;
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bb_q_min = 18'sh1FFFF;
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// Run for 4000 clocks at 400 MHz
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// CIC decimates 4x, CDC adds latency, FIR adds 32 taps
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// Expect first output after ~50+ clocks, then continuous
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for (sample_count = 0; sample_count < 4000; sample_count = sample_count + 1) begin
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// 120 MHz tone in 8-bit unsigned: 128 + 100*sin(2*pi*120/400*n)
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adc_data = 128 + $rtoi(100.0 * $sin(6.2831853 * 120.0 / 400.0 * sample_count));
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@(posedge clk_400m); #1;
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if (baseband_valid_i && baseband_valid_q) begin
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$fwrite(csv_file, "%0d,%0d,%0d,%0d,1\n",
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sample_count, adc_data, baseband_i, baseband_q);
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output_count = output_count + 1;
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if (output_count > 50) begin // skip transient
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if (baseband_i > bb_i_max) bb_i_max = baseband_i;
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if (baseband_i < bb_i_min) bb_i_min = baseband_i;
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if (baseband_q > bb_q_max) bb_q_max = baseband_q;
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if (baseband_q < bb_q_min) bb_q_min = baseband_q;
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end
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end
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end
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$fclose(csv_file);
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$display(" 120 MHz IF: %0d baseband outputs", output_count);
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$display(" BB I range: [%0d, %0d]", bb_i_min, bb_i_max);
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$display(" BB Q range: [%0d, %0d]", bb_q_min, bb_q_max);
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$display(" DDC status: %b, diagnostics: %h", ddc_status, ddc_diagnostics);
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check(output_count > 0, "DDC chain produces baseband output");
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check(ddc_status[0] === 1'b1, "NCO ready (ddc_status[0])");
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// ════════════════════════════════════════════════════════
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// TEST GROUP 3: Off-frequency tone (should be attenuated)
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// ════════════════════════════════════════════════════════
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$display("\n--- Test Group 3: Off-Frequency Tone (150 MHz) ---");
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reset_n = 0;
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mixers_enable = 0;
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adc_data_valid_i = 0;
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adc_data_valid_q = 0;
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repeat (20) @(posedge clk_400m);
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reset_n = 1;
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repeat (10) @(posedge clk_400m);
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mixers_enable = 1;
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adc_data_valid_i = 1;
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adc_data_valid_q = 1;
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output_count = 0;
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bb_i_max = -18'sh1FFFF;
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bb_i_min = 18'sh1FFFF;
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// 150 MHz tone — 30 MHz away from 120 MHz IF
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// After mixing, this becomes a 30 MHz baseband signal
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// CIC + FIR should pass or attenuate depending on their bandwidth
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for (sample_count = 0; sample_count < 4000; sample_count = sample_count + 1) begin
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adc_data = 128 + $rtoi(100.0 * $sin(6.2831853 * 150.0 / 400.0 * sample_count));
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@(posedge clk_400m); #1;
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if (baseband_valid_i && baseband_valid_q) begin
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output_count = output_count + 1;
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if (output_count > 50) begin
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if (baseband_i > bb_i_max) bb_i_max = baseband_i;
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if (baseband_i < bb_i_min) bb_i_min = baseband_i;
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end
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end
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end
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$display(" 150 MHz IF: %0d outputs, BB I range [%0d, %0d]",
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output_count, bb_i_min, bb_i_max);
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check(output_count > 0, "DDC produces output for off-frequency tone");
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// ════════════════════════════════════════════════════════
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// TEST GROUP 4: Debug sample counter
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// ════════════════════════════════════════════════════════
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$display("\n--- Test Group 4: Debug Counters ---");
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$display(" debug_sample_count = %0d", debug_sample_count);
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check(debug_sample_count > 0, "Sample counter increments");
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// ════════════════════════════════════════════════════════
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// Summary
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// ════════════════════════════════════════════════════════
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$display("");
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$display("========================================");
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$display(" DDC 400M CHAIN TESTBENCH RESULTS");
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$display(" PASSED: %0d / %0d", pass_count, test_num);
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$display(" FAILED: %0d / %0d", fail_count, test_num);
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if (fail_count == 0)
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$display(" ** ALL TESTS PASSED **");
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else
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$display(" ** SOME TESTS FAILED **");
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$display("========================================");
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$display("");
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#100;
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$finish;
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end
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endmodule
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