683e70e784
- Changed user_led/system_status IOSTANDARD from LVCMOS25 to LVCMOS33 to match VIOTB=3.3V needed for FT601 on Bank 16 - Added register init value for hb_counter - Added comments documenting clock source (50 MHz FIFO0CLK at U20, Bank 14) and expected LED toggle rates
58 lines
2.6 KiB
Tcl
58 lines
2.6 KiB
Tcl
# ============================================================================
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# AERIS-10 TE0713/TE0701 DEV TARGET (MINIMAL SPLIT)
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# ============================================================================
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# Target part: XC7A200T-2FBG484C (TE0713-03-82C46-A)
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# Board: TE0701-06 carrier
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#
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# This XDC is intentionally minimal and is used with:
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# top = radar_system_top_te0713_dev
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#
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# Notes:
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# - TE0713 clock routing differs from TE0712. This target uses FIFO0CLK net at
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# package pin U20 as primary fabric clock for initial bring-up.
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# - No external reset is used in this minimal top to avoid uncertain reset pin
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# assumptions between TE0712/TE0713 revisions.
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# ============================================================================
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design]
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# Clock IOSTANDARD
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set_property IOSTANDARD LVCMOS15 [get_ports {clk_100m}]
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# Status/output IO standards
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# These outputs are exported to TE0701 FMC LA lines (not onboard LEDs).
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# Bank 16 VCCO = VIOTB on TE0701, set to 3.3V for FT601 compatibility.
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set_property IOSTANDARD LVCMOS33 [get_ports {user_led[*]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {system_status[*]}]
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# Clock constraint (TE0713 FIFO0CLK source observed as 50 MHz)
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create_clock -name clk_100m -period 20.000 [get_ports {clk_100m}]
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set_input_jitter [get_clocks clk_100m] 0.100
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# --------------------------------------------------------------------------
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# TE0713 package pin mapping
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# --------------------------------------------------------------------------
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set_property PACKAGE_PIN U20 [get_ports {clk_100m}]
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# --------------------------------------------------------------------------
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# TE0701 FMC export mapping (B16 bank mappings align with TE0712 flow)
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# user_led[0..3] -> FMC_LA14_N/P, FMC_LA13_N/P
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# system_status[] -> FMC_LA5_N/P, FMC_LA6_N/P
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# --------------------------------------------------------------------------
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set_property PACKAGE_PIN A19 [get_ports {user_led[0]}]
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set_property PACKAGE_PIN A18 [get_ports {user_led[1]}]
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set_property PACKAGE_PIN F20 [get_ports {user_led[2]}]
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set_property PACKAGE_PIN F19 [get_ports {user_led[3]}]
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set_property PACKAGE_PIN F18 [get_ports {system_status[0]}]
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set_property PACKAGE_PIN E18 [get_ports {system_status[1]}]
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set_property PACKAGE_PIN C22 [get_ports {system_status[2]}]
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set_property PACKAGE_PIN B22 [get_ports {system_status[3]}]
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# --------------------------------------------------------------------------
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# Keep implementation checks strict.
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# report_timing_summary -report_unconstrained
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# report_drc
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