c983a3c705
Phase 0+ timing optimization (attempts #13-22 + implementation): NCO (nco_400m_enhanced.v): - 4-stage pipeline: DSP48E1 accumulate -> LUT read -> negate -> quadrant MUX - DSP48E1 phase accumulator in P=P+C mode (eliminates 8-stage CARRY4 chain) - Registered phase_inc_dithered to break cascaded 32-bit add path DDC (ddc_400m.v): - Direct DSP48E1 instantiation for I/Q mixers (AREG=1, BREG=1, MREG=1, PREG=1) - CEP=1, RSTP=!reset_n for proper pipeline control - 3-stage dsp_valid_pipe for PREG=1 latency - Behavioral sim model under ifdef SIMULATION for Icarus compatibility CIC (cic_decimator_4x_enhanced.v): - 28-bit accumulators (was 36) per CIC width formula: 18 + 5*log2(4) = 28 - Removed integrator/comb saturation (CIC uses wrapping arithmetic by design) - Pipelined output saturation comparison CDC/ASYNC_REG: - ASYNC_REG attribute on all CDC synchronizer registers (cdc_modules.v, radar_system_top.v, usb_data_interface.v) - Sync reset in generate blocks (cdc_modules.v) Results: Vivado post-implementation WNS=+1.196ns, 0 failing endpoints, 850 LUTs (1.34%), 466 FFs (0.37%), 2 DSP48E1 (0.83%) on xc7a100t. All testbenches pass: 241/244 (3 known stub failures).
133 B
133 B
| 1 | sample | data_out |
|---|---|---|
| 2 | 0 | 0 |
| 3 | 1 | 0 |
| 4 | 2 | 0 |
| 5 | 3 | 0 |
| 6 | 4 | 0 |
| 7 | 5 | 0 |
| 8 | 6 | 9 |
| 9 | 7 | 634 |
| 10 | 8 | 1513 |
| 11 | 9 | 341 |
| 12 | 10 | 0 |
| 13 | 11 | 0 |
| 14 | 12 | 0 |
| 15 | 13 | 0 |
| 16 | 14 | 0 |
| 17 | 15 | 0 |
| 18 | 16 | 0 |
| 19 | 17 | 0 |
| 20 | 18 | 0 |
| 21 | 19 | 0 |
| 22 | 20 | 0 |
| 23 | 21 | 0 |
| 24 | 22 | 0 |
| 25 | 23 | 0 |