Jason
baa24fd01e
Bit-accurate Python model (fpga_model.py) mirrors full DDC RTL chain: NCO -> mixer -> CIC -> FIR with exact fixed-point arithmetic matching RTL DSP48E1 pipeline behavior including CREG=1 delay on CIC int_0. Synthetic radar scene generator (radar_scene.py) produces ADC test vectors for 5 scenarios: DC, single target (500m), multi-target (5), noise-only, and 1 MHz sine wave. DDC co-sim testbench (tb_ddc_cosim.v) feeds hex vectors through RTL DDC and exports baseband I/Q to CSV. All 5 scenarios compile and run with Icarus Verilog (iverilog -g2001 -DSIMULATION). Comparison framework (compare.py) validates Python vs RTL using statistical metrics (RMS ratio, DC offset, peak ratio) rather than exact sample match due to RTL LFSR phase dithering. Results: 5/5 PASS.
31 lines
994 B
Plaintext
31 lines
994 B
Plaintext
AERIS-10 Test Vector Scenarios
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System Parameters:
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Carrier: 10.5 GHz
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IF: 120 MHz
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Chirp BW: 20 MHz
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ADC: 400 MSPS, 8-bit
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Range resolution: 7.5 m
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Wavelength: 28.57 mm
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Scenario 1: Single target
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Target(range=500.0m, vel=0.0m/s, RCS=0.0dBsm, delay=1333.3samp)
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Scenario 2: Multi-target (5 targets)
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Target(range=100.0m, vel=0.0m/s, RCS=20.0dBsm, delay=266.7samp)
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Target(range=500.0m, vel=30.0m/s, RCS=10.0dBsm, delay=1333.3samp)
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Target(range=1000.0m, vel=-15.0m/s, RCS=5.0dBsm, delay=2666.7samp)
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Target(range=2000.0m, vel=50.0m/s, RCS=0.0dBsm, delay=5333.3samp)
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Target(range=5000.0m, vel=-5.0m/s, RCS=-5.0dBsm, delay=13333.3samp)
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Scenario 3: Noise only (stddev=5.0 LSB)
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Scenario 4: DC input (value=128)
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Scenario 5: 1 MHz sine wave (amplitude=50 LSB)
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Baseband MF test targets:
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Target(range=500.0m, vel=0.0m/s, RCS=10.0dBsm, delay=1333.3samp)
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Target(range=1500.0m, vel=20.0m/s, RCS=5.0dBsm, delay=4000.0samp)
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