baa24fd01e
Bit-accurate Python model (fpga_model.py) mirrors full DDC RTL chain: NCO -> mixer -> CIC -> FIR with exact fixed-point arithmetic matching RTL DSP48E1 pipeline behavior including CREG=1 delay on CIC int_0. Synthetic radar scene generator (radar_scene.py) produces ADC test vectors for 5 scenarios: DC, single target (500m), multi-target (5), noise-only, and 1 MHz sine wave. DDC co-sim testbench (tb_ddc_cosim.v) feeds hex vectors through RTL DDC and exports baseband I/Q to CSV. All 5 scenarios compile and run with Icarus Verilog (iverilog -g2001 -DSIMULATION). Comparison framework (compare.py) validates Python vs RTL using statistical metrics (RMS ratio, DC offset, peak ratio) rather than exact sample match due to RTL LFSR phase dithering. Results: 5/5 PASS.
228 B
228 B
| 1 | sample | data_out |
|---|---|---|
| 2 | 0 | 1 |
| 3 | 1 | 1 |
| 4 | 2 | -5 |
| 5 | 3 | 5 |
| 6 | 4 | 1 |
| 7 | 5 | -15 |
| 8 | 6 | 20 |
| 9 | 7 | -5 |
| 10 | 8 | -30 |
| 11 | 9 | 56 |
| 12 | 10 | -35 |
| 13 | 11 | -47 |
| 14 | 12 | 141 |
| 15 | 13 | -150 |
| 16 | 14 | -58 |
| 17 | 15 | 999 |
| 18 | 16 | 999 |
| 19 | 17 | -58 |
| 20 | 18 | -150 |
| 21 | 19 | 141 |
| 22 | 20 | -47 |
| 23 | 21 | -35 |
| 24 | 22 | 56 |
| 25 | 23 | -30 |
| 26 | 24 | -5 |
| 27 | 25 | 20 |
| 28 | 26 | -15 |
| 29 | 27 | 1 |
| 30 | 28 | 5 |
| 31 | 29 | -5 |
| 32 | 30 | 1 |
| 33 | 31 | 1 |
| 34 | 32 | 0 |
| 35 | 33 | 0 |
| 36 | 34 | 0 |
| 37 | 35 | 0 |