b823d83feb
New testbenches: - tb_latency_buffer.v: 13/13 tests for BRAM delay line (P1-3) - tb_cdc_modules.v: 27/27 tests for all 3 CDC primitives (P1-4) - tb_ad9484_xsim.v: XSim testbench for AD9484 with Xilinx BUFIO/IDDR - tb_nco_xsim.v: XSim testbench for NCO DSP48E1 path verification Fixes: - tb_usb_data_interface.v: updated test 33 from divide-by-2 check to ODDR-style clock forwarding verification (39/39 pass) - rx_final_doppler_out.csv: updated golden reference after bug fixes
316 lines
14 KiB
Verilog
316 lines
14 KiB
Verilog
`timescale 1ns / 1ps
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// ============================================================================
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// tb_ad9484_xsim.v — XSim testbench for ad9484_interface_400m.v
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//
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// Tests the REAL module with Xilinx UNISIM primitives (IBUFDS, BUFG, IDDR).
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// Must be compiled with xvlog/xelab/xsim (not iverilog).
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//
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// Key things tested:
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// 1. Differential LVDS data capture (IBUFDS)
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// 2. DDR data capture (IDDR, SAME_EDGE_PIPELINED mode)
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// 3. Reset synchronizer (P1-7 fix: async assert, sync de-assert)
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// 4. Data integrity through full pipeline
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// 5. Phase interleaving (rising/falling edge multiplexing)
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// ============================================================================
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module tb_ad9484_xsim;
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// ── Parameters ─────────────────────────────────────────────
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localparam DCO_PERIOD = 2.5; // 400 MHz
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localparam SYS_PERIOD = 10.0; // 100 MHz
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// ── Signals ────────────────────────────────────────────────
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// LVDS pairs (differential)
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reg [7:0] adc_d_p;
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wire [7:0] adc_d_n;
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reg adc_dco_p;
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wire adc_dco_n;
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// System
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reg sys_clk;
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reg reset_n;
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// Outputs
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wire [7:0] adc_data_400m;
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wire adc_data_valid_400m;
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wire adc_dco_bufg;
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// Differential complements
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assign adc_d_n = ~adc_d_p;
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assign adc_dco_n = ~adc_dco_p;
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// ── Test bookkeeping ───────────────────────────────────────
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integer pass_count;
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integer fail_count;
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integer test_num;
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integer i;
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// ── Clocks ─────────────────────────────────────────────────
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always #(DCO_PERIOD/2) adc_dco_p = ~adc_dco_p;
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always #(SYS_PERIOD/2) sys_clk = ~sys_clk;
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// ── DUT ────────────────────────────────────────────────────
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ad9484_interface_400m uut (
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.adc_d_p (adc_d_p),
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.adc_d_n (adc_d_n),
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.adc_dco_p (adc_dco_p),
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.adc_dco_n (adc_dco_n),
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.sys_clk (sys_clk),
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.reset_n (reset_n),
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.adc_data_400m (adc_data_400m),
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.adc_data_valid_400m(adc_data_valid_400m),
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.adc_dco_bufg (adc_dco_bufg)
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);
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// ── Check task ─────────────────────────────────────────────
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task check;
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input cond;
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input [511:0] label;
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begin
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test_num = test_num + 1;
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if (cond) begin
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$display("[PASS] Test %0d: %0s", test_num, label);
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pass_count = pass_count + 1;
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end else begin
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$display("[FAIL] Test %0d: %0s", test_num, label);
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fail_count = fail_count + 1;
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end
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end
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endtask
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// ── Stimulus ───────────────────────────────────────────────
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initial begin
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$display("\n=== AD9484 Interface XSim Testbench ===");
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$display(" Testing REAL Xilinx primitives (IBUFDS, BUFG, IDDR)");
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$display(" Testing reset synchronizer (P1-7 fix)\n");
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// Init
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adc_dco_p = 0;
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sys_clk = 0;
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adc_d_p = 8'h00;
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reset_n = 0;
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pass_count = 0;
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fail_count = 0;
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test_num = 0;
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// ════════════════════════════════════════════════════════
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// TEST GROUP 1: Reset behaviour
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// ════════════════════════════════════════════════════════
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$display("--- Test Group 1: Reset Behaviour ---");
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#50; // let clocks run during reset
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check(adc_data_valid_400m === 1'b0, "valid = 0 during reset");
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check(adc_data_400m === 8'h00, "data = 0 during reset");
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// ════════════════════════════════════════════════════════
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// TEST GROUP 2: BUFG clock output
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// ════════════════════════════════════════════════════════
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$display("\n--- Test Group 2: Clock Buffering ---");
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// adc_dco_bufg should follow adc_dco_p (through BUFG)
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// Can't check exact timing but can verify it toggles
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begin : bufg_test
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reg saw_high, saw_low;
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saw_high = 0;
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saw_low = 0;
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for (i = 0; i < 20; i = i + 1) begin
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#(DCO_PERIOD/4);
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if (adc_dco_bufg) saw_high = 1;
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else saw_low = 1;
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end
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check(saw_high && saw_low, "adc_dco_bufg toggles (BUFG functional)");
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end
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// ════════════════════════════════════════════════════════
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// TEST GROUP 3: Reset de-assertion synchronization (P1-7)
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// ════════════════════════════════════════════════════════
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$display("\n--- Test Group 3: Reset Synchronizer (P1-7) ---");
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// De-assert reset BETWEEN dco edges (worst case for metastability)
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// The synchronizer should delay de-assertion by 2 dco cycles
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@(negedge adc_dco_p);
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#(DCO_PERIOD * 0.3); // mid-cycle
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reset_n = 1;
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// valid should NOT assert immediately (needs 2 sync stages)
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@(posedge adc_dco_p); #0.1;
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// After 1 dco cycle: reset_sync_400m[0] = 1, [1] still = 0
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// So reset_n_400m should still be 0
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check(adc_data_valid_400m === 1'b0,
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"valid stays 0 for 1 cycle after reset de-assert (sync stage 1)");
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@(posedge adc_dco_p); #0.1;
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// After 2 dco cycles: reset_sync_400m = 2'b11, reset_n_400m = 1
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// But the data pipeline has its own 1-cycle delay
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// So valid might assert this cycle or next
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// Wait one more cycle for pipeline
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@(posedge adc_dco_p); #0.1;
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// By now (3 dco cycles after reset de-assert), valid should be 1
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// Allow one more for IDDR pipeline
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begin : wait_valid
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reg saw_valid;
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saw_valid = 0;
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for (i = 0; i < 5; i = i + 1) begin
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@(posedge adc_dco_p); #0.1;
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if (adc_data_valid_400m) begin
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saw_valid = 1;
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$display(" valid asserted %0d dco cycles after reset de-assert", i + 4);
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disable wait_valid;
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end
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end
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if (!saw_valid) begin
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$display(" [WARN] valid did not assert within 8 dco cycles");
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end
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end
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check(adc_data_valid_400m === 1'b1,
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"valid asserts after reset sync pipeline completes");
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// ════════════════════════════════════════════════════════
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// TEST GROUP 4: Data capture via IDDR
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// ════════════════════════════════════════════════════════
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$display("\n--- Test Group 4: IDDR Data Capture ---");
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// Reset and restart
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reset_n = 0;
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adc_d_p = 8'h00;
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#100;
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reset_n = 1;
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// Wait for reset sync pipeline
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repeat (5) @(posedge adc_dco_p);
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// Feed a known pattern on rising edges
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// IDDR in SAME_EDGE_PIPELINED mode captures:
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// Q1 = data at rising edge (1 cycle pipelined)
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// Q2 = data at falling edge (pipelined to align with Q1)
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// The module alternates output between Q1 and Q2 via dco_phase
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// Drive known data: alternate 0xAA on rise, 0x55 on fall
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begin : iddr_test
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reg [7:0] captured [0:31];
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integer cap_count;
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integer saw_aa, saw_55;
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cap_count = 0;
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saw_aa = 0;
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saw_55 = 0;
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for (i = 0; i < 20; i = i + 1) begin
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// Set data before rising edge
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adc_d_p = 8'hAA;
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@(posedge adc_dco_p);
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// Set data before falling edge
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#0.1;
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adc_d_p = 8'h55;
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@(negedge adc_dco_p);
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#0.1;
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// Capture output
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if (adc_data_valid_400m && cap_count < 32) begin
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captured[cap_count] = adc_data_400m;
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if (adc_data_400m == 8'hAA) saw_aa = saw_aa + 1;
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if (adc_data_400m == 8'h55) saw_55 = saw_55+ 1;
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cap_count = cap_count + 1;
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end
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end
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$display(" Captured %0d samples, saw 0xAA: %0d times, 0x55: %0d times",
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cap_count, saw_aa, saw_55);
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check(cap_count > 0, "IDDR produces output samples");
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// With DDR capture, we should see both rise and fall data
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check(saw_aa > 0 || saw_55 > 0, "IDDR captures at least one known value");
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end
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// ════════════════════════════════════════════════════════
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// TEST GROUP 5: Sequential data integrity
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// ════════════════════════════════════════════════════════
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$display("\n--- Test Group 5: Sequential Data Integrity ---");
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reset_n = 0;
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#100;
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reset_n = 1;
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repeat (5) @(posedge adc_dco_p);
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// Feed incrementing pattern: 0, 1, 2, ... on each half-cycle
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begin : seq_test
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reg [7:0] outputs [0:63];
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integer out_count;
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reg saw_nonzero;
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reg monotonic;
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out_count = 0;
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saw_nonzero = 0;
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for (i = 0; i < 40; i = i + 1) begin
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adc_d_p = i[7:0];
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@(posedge adc_dco_p); #0.1;
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if (adc_data_valid_400m && out_count < 64) begin
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outputs[out_count] = adc_data_400m;
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if (adc_data_400m != 0) saw_nonzero = 1;
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out_count = out_count + 1;
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end
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end
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$display(" Sequential: captured %0d outputs, saw_nonzero=%b",
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out_count, saw_nonzero);
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check(out_count > 10, "Produces substantial output stream");
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check(saw_nonzero, "Output contains non-zero values");
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end
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// ════════════════════════════════════════════════════════
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// TEST GROUP 6: Reset mid-operation
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// ════════════════════════════════════════════════════════
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$display("\n--- Test Group 6: Reset Mid-Operation ---");
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// Data should be flowing now
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adc_d_p = 8'hFF;
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repeat (5) @(posedge adc_dco_p);
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// Assert reset asynchronously (should take effect immediately)
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reset_n = 0;
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// The async assert should clear valid within 1 cycle
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repeat (2) @(posedge adc_dco_p); #0.1;
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check(adc_data_valid_400m === 1'b0, "Async reset assertion clears valid immediately");
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check(adc_data_400m === 8'h00, "Async reset assertion clears data to 0");
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// De-assert and verify sync pipeline
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#30;
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reset_n = 1;
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// Should NOT be valid yet (2-stage sync)
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@(posedge adc_dco_p); #0.1;
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check(adc_data_valid_400m === 1'b0,
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"valid stays 0 during reset sync de-assertion");
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// Wait for full pipeline
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repeat (5) @(posedge adc_dco_p); #0.1;
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check(adc_data_valid_400m === 1'b1,
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"valid reasserts after sync pipeline completes");
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// ════════════════════════════════════════════════════════
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// TEST GROUP 7: ADC power-down output
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// ════════════════════════════════════════════════════════
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// adc_pwdn is not part of this module (it's in radar_system_top)
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// Just verify the module port list is complete
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// ════════════════════════════════════════════════════════
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// Summary
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// ════════════════════════════════════════════════════════
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$display("");
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$display("========================================");
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$display(" AD9484 INTERFACE XSIM RESULTS");
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$display(" PASSED: %0d / %0d", pass_count, test_num);
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$display(" FAILED: %0d / %0d", fail_count, test_num);
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if (fail_count == 0)
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$display(" ** ALL TESTS PASSED **");
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else
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$display(" ** SOME TESTS FAILED **");
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$display("========================================");
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$display("");
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#100;
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$finish;
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end
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endmodule
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