fcf3999e39
Split cdc_adc_to_processing reset_n into src_reset_n/dst_reset_n so source and destination clock domains use correctly-synchronized resets. Previously cdc_chirp_counter's destination-side sync chain (100MHz) was reset by sys_reset_120m_n (120MHz domain), causing 30 CDC critical warnings. RTL changes: - cdc_modules.v: split reset port, source logic uses src_reset_n, destination sync chains + output logic use dst_reset_n - radar_system_top.v: cdc_chirp_counter gets proper per-domain resets - ddc_400m.v: CDC_FIR_i/q use reset_n_400m (src) and reset_n (dst) - formal/fv_cdc_adc.v: updated wrapper for new port interface Build 7 fixes (previously untouched): - radar_transmitter.v: SPI level-shifter assigns, STM32 GPIO CDC sync - latency_buffer_2159.v: BRAM read registration - constraints: ft601 IOB -quiet fix - tb_latency_buffer.v: updated for BRAM changes Testbench hardening (tb_cdc_modules.v, +31 new assertions): - A5-A7: split-domain reset tests (staggered deassertion, independent dst reset while src active — catches the P0 bug class) - A8: port connectivity (no X/Z on outputs) - B7: cdc_single_bit port connectivity - C6: cdc_handshake reset recovery + port connectivity Full regression: 13/13 test suites pass (257 total assertions).
897 lines
36 KiB
Verilog
897 lines
36 KiB
Verilog
`timescale 1ns / 1ps
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module tb_cdc_modules;
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// ── Clock periods (reflecting real system) ─────────────────
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localparam SRC_CLK_PERIOD = 2.5; // 400 MHz (ADC domain)
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localparam DST_CLK_PERIOD = 10.0; // 100 MHz (processing domain)
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// For handshake tests, use different ratio
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localparam HS_SRC_PERIOD = 10.0; // 100 MHz
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localparam HS_DST_PERIOD = 7.0; // ~143 MHz (non-integer ratio)
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// ── Test bookkeeping ───────────────────────────────────────
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integer pass_count;
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integer fail_count;
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integer test_num;
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integer i;
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// ── Check task ─────────────────────────────────────────────
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task check;
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input cond;
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input [511:0] label;
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begin
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test_num = test_num + 1;
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if (cond) begin
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$display("[PASS] Test %0d: %0s", test_num, label);
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pass_count = pass_count + 1;
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end else begin
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$display("[FAIL] Test %0d: %0s", test_num, label);
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fail_count = fail_count + 1;
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end
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end
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endtask
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// ════════════════════════════════════════════════════════════
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// MODULE 1: cdc_adc_to_processing (Gray-code multi-bit CDC)
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// ════════════════════════════════════════════════════════════
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reg m1_src_clk;
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reg m1_dst_clk;
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reg m1_src_reset_n;
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reg m1_dst_reset_n;
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reg [7:0] m1_src_data;
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reg m1_src_valid;
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wire [7:0] m1_dst_data;
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wire m1_dst_valid;
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always #(SRC_CLK_PERIOD/2) m1_src_clk = ~m1_src_clk;
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always #(DST_CLK_PERIOD/2) m1_dst_clk = ~m1_dst_clk;
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cdc_adc_to_processing #(
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.WIDTH(8),
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.STAGES(3)
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) uut_m1 (
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.src_clk (m1_src_clk),
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.dst_clk (m1_dst_clk),
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.src_reset_n (m1_src_reset_n),
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.dst_reset_n (m1_dst_reset_n),
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.src_data (m1_src_data),
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.src_valid (m1_src_valid),
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.dst_data (m1_dst_data),
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.dst_valid (m1_dst_valid)
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);
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// ════════════════════════════════════════════════════════════
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// MODULE 2: cdc_single_bit
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// ════════════════════════════════════════════════════════════
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reg m2_src_clk;
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reg m2_dst_clk;
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reg m2_reset_n;
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reg m2_src_signal;
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wire m2_dst_signal;
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always #(SRC_CLK_PERIOD/2) m2_src_clk = ~m2_src_clk;
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always #(DST_CLK_PERIOD/2) m2_dst_clk = ~m2_dst_clk;
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cdc_single_bit #(
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.STAGES(3)
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) uut_m2 (
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.src_clk (m2_src_clk),
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.dst_clk (m2_dst_clk),
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.reset_n (m2_reset_n),
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.src_signal(m2_src_signal),
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.dst_signal(m2_dst_signal)
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);
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// ════════════════════════════════════════════════════════════
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// MODULE 3: cdc_handshake
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// ════════════════════════════════════════════════════════════
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reg m3_src_clk;
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reg m3_dst_clk;
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reg m3_reset_n;
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reg [31:0] m3_src_data;
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reg m3_src_valid;
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wire m3_src_ready;
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wire [31:0] m3_dst_data;
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wire m3_dst_valid;
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reg m3_dst_ready;
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always #(HS_SRC_PERIOD/2) m3_src_clk = ~m3_src_clk;
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always #(HS_DST_PERIOD/2) m3_dst_clk = ~m3_dst_clk;
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cdc_handshake #(
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.WIDTH(32)
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) uut_m3 (
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.src_clk (m3_src_clk),
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.dst_clk (m3_dst_clk),
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.reset_n (m3_reset_n),
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.src_data (m3_src_data),
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.src_valid(m3_src_valid),
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.src_ready(m3_src_ready),
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.dst_data (m3_dst_data),
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.dst_valid(m3_dst_valid),
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.dst_ready(m3_dst_ready)
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);
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// ── Main test sequence ─────────────────────────────────────
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initial begin
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$dumpfile("tb_cdc_modules.vcd");
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$dumpvars(0, tb_cdc_modules);
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// Init all clocks and signals
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m1_src_clk = 0; m1_dst_clk = 0;
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m1_src_reset_n = 0; m1_dst_reset_n = 0;
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m1_src_data = 0; m1_src_valid = 0;
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m2_src_clk = 0; m2_dst_clk = 0; m2_reset_n = 0;
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m2_src_signal = 0;
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m3_src_clk = 0; m3_dst_clk = 0; m3_reset_n = 0;
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m3_src_data = 0; m3_src_valid = 0; m3_dst_ready = 0;
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pass_count = 0; fail_count = 0; test_num = 0;
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// ════════════════════════════════════════════════════════
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// SECTION A: cdc_adc_to_processing tests
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// ════════════════════════════════════════════════════════
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$display("\n=== Section A: cdc_adc_to_processing (Gray-code CDC) ===");
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// ── A1: Reset behaviour ────────────────────────────────
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$display("\n--- A1: Reset Behaviour (split-domain reset) ---");
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m1_src_reset_n = 0; m1_dst_reset_n = 0;
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#100; // let both clocks run
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check(m1_dst_valid === 1'b0, "M1: dst_valid = 0 during reset");
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check(m1_dst_data === 8'd0, "M1: dst_data = 0 during reset");
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// Release reset
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@(posedge m1_dst_clk);
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m1_src_reset_n = 1; m1_dst_reset_n = 1;
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@(posedge m1_src_clk);
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// ── A2: Single value transfer ──────────────────────────
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$display("\n--- A2: Single Value Transfer ---");
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m1_src_data = 8'hA5;
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m1_src_valid = 1;
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@(posedge m1_src_clk); #1;
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m1_src_valid = 0;
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// Wait for CDC propagation (3 stages × dst_clk + margin)
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begin : a2_wait
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integer wait_cycles;
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reg saw_valid;
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saw_valid = 0;
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for (wait_cycles = 0; wait_cycles < 20; wait_cycles = wait_cycles + 1) begin
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@(posedge m1_dst_clk); #1;
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if (m1_dst_valid) begin
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saw_valid = 1;
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disable a2_wait;
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end
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end
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end
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check(m1_dst_valid === 1'b1, "M1: dst_valid asserts after CDC");
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check(m1_dst_data === 8'hA5, "M1: data 0xA5 transferred correctly");
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// ── A3: Multiple sequential values ─────────────────────
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$display("\n--- A3: Multiple Sequential Values ---");
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m1_src_reset_n = 0; m1_dst_reset_n = 0;
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#100;
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m1_src_reset_n = 1; m1_dst_reset_n = 1;
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@(posedge m1_src_clk);
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begin : a3_block
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reg [7:0] received_values [0:31];
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integer rx_count;
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integer tx_count;
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integer total_wait;
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reg all_received;
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rx_count = 0;
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// Send 8 values, one per src_clk cycle
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// At 400:100 ratio, src sends 4x faster than dst can sample
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// Gray-code CDC may miss intermediate values — that's expected.
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// What matters is that received values are VALID (not corrupted).
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for (tx_count = 0; tx_count < 8; tx_count = tx_count + 1) begin
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m1_src_data = tx_count * 37 + 10; // 10, 47, 84, 121, 158, 195, 232, 13
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m1_src_valid = 1;
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@(posedge m1_src_clk); #1;
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end
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m1_src_valid = 0;
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// Collect outputs
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for (total_wait = 0; total_wait < 40; total_wait = total_wait + 1) begin
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@(posedge m1_dst_clk); #1;
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if (m1_dst_valid) begin
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received_values[rx_count] = m1_dst_data;
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rx_count = rx_count + 1;
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end
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end
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$display(" Sent 8 values at 400MHz, received %0d valid values at 100MHz",
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rx_count);
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check(rx_count > 0, "M1: At least one value received from burst");
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// Verify last received value matches last sent value
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// (The CDC should eventually stabilize to the last written value)
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if (rx_count > 0) begin
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// Check that every received value is one of the sent values
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begin : verify_received
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reg [7:0] sent_vals [0:7];
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reg found;
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integer j, k;
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reg all_valid;
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for (j = 0; j < 8; j = j + 1) begin
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sent_vals[j] = j * 37 + 10;
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end
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all_valid = 1;
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for (j = 0; j < rx_count; j = j + 1) begin
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found = 0;
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for (k = 0; k < 8; k = k + 1) begin
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if (received_values[j] === sent_vals[k]) found = 1;
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end
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if (!found) begin
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all_valid = 0;
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$display(" [WARN] Received value 0x%02x not in sent set",
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received_values[j]);
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end
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end
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check(all_valid, "M1: All received values are valid (no corruption)");
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end
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end else begin
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check(1'b0, "M1: All received values are valid (no corruption)");
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end
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end
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// ── A4: Slow sender (one value every 4 dst_clk cycles) ─
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$display("\n--- A4: Slow Sender ---");
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m1_src_reset_n = 0; m1_dst_reset_n = 0;
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#100;
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m1_src_reset_n = 1; m1_dst_reset_n = 1;
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@(posedge m1_src_clk);
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begin : a4_block
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reg [7:0] expected_vals [0:7];
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reg [7:0] got_vals [0:7];
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integer tx_idx, rx_idx, wait_cnt;
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reg all_match;
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rx_idx = 0;
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for (tx_idx = 0; tx_idx < 4; tx_idx = tx_idx + 1) begin
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expected_vals[tx_idx] = (tx_idx + 1) * 50; // 50, 100, 150, 200
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m1_src_data = expected_vals[tx_idx];
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m1_src_valid = 1;
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@(posedge m1_src_clk); #1;
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m1_src_valid = 0;
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// Wait long enough for CDC to propagate
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for (wait_cnt = 0; wait_cnt < 15; wait_cnt = wait_cnt + 1) begin
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@(posedge m1_dst_clk); #1;
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if (m1_dst_valid && rx_idx < 8) begin
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got_vals[rx_idx] = m1_dst_data;
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rx_idx = rx_idx + 1;
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end
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end
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end
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$display(" Slow send: sent 4, received %0d", rx_idx);
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check(rx_idx == 4, "M1: All 4 slow-sent values received");
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all_match = 1;
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for (i = 0; i < rx_idx && i < 4; i = i + 1) begin
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if (got_vals[i] !== expected_vals[i]) begin
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all_match = 0;
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$display(" [WARN] Slow rx[%0d]: got 0x%02x, exp 0x%02x",
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i, got_vals[i], expected_vals[i]);
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end
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end
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check(all_match, "M1: Slow-sent values match exactly");
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end
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// ── A5: Split-Domain Reset — Src resets while dst stays active ──
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$display("\n--- A5: Split-Domain Reset (src resets, dst active) ---");
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m1_src_reset_n = 0; m1_dst_reset_n = 0;
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m1_src_data = 0; m1_src_valid = 0;
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#100;
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// Release dst_reset_n first, src stays in reset
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m1_dst_reset_n = 1;
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begin : a5_dst_idle
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integer wait_cycles;
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reg saw_valid;
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saw_valid = 0;
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for (wait_cycles = 0; wait_cycles < 10; wait_cycles = wait_cycles + 1) begin
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@(posedge m1_dst_clk); #1;
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if (m1_dst_valid) saw_valid = 1;
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end
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check(!saw_valid, "M1: dst_valid stays 0 while src is in reset");
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end
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// Now release src_reset_n
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m1_src_reset_n = 1;
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@(posedge m1_src_clk);
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// Send data and verify transfer works after staggered reset
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m1_src_data = 8'h3C;
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m1_src_valid = 1;
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@(posedge m1_src_clk); #1;
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m1_src_valid = 0;
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begin : a5_wait
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integer wait_cycles;
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for (wait_cycles = 0; wait_cycles < 20; wait_cycles = wait_cycles + 1) begin
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@(posedge m1_dst_clk); #1;
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if (m1_dst_valid) disable a5_wait;
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end
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end
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check(m1_dst_valid === 1'b1, "M1: dst_valid asserts after staggered src reset release");
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check(m1_dst_data === 8'h3C, "M1: data 0x3C correct after staggered src reset");
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// ── A6: Split-Domain Reset — Dst resets while src stays active ──
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// KEY test: catches the original P0 bug where a single reset from
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// the src domain was used to reset dst-domain registers.
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$display("\n--- A6: Split-Domain Reset (dst resets, src active) ---");
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m1_src_reset_n = 1; m1_dst_reset_n = 1;
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m1_src_data = 0; m1_src_valid = 0;
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@(posedge m1_src_clk);
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// Send data and verify it arrives (baseline)
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m1_src_data = 8'hF0;
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m1_src_valid = 1;
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@(posedge m1_src_clk); #1;
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m1_src_valid = 0;
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begin : a6_baseline
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integer wait_cycles;
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for (wait_cycles = 0; wait_cycles < 20; wait_cycles = wait_cycles + 1) begin
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@(posedge m1_dst_clk); #1;
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if (m1_dst_valid) disable a6_baseline;
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end
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end
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check(m1_dst_data === 8'hF0, "M1: Baseline data 0xF0 received before dst-only reset");
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// Assert ONLY dst_reset_n (src keeps running)
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m1_dst_reset_n = 0;
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begin : a6_check_reset
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integer wait_cycles;
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reg dst_cleared;
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dst_cleared = 0;
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for (wait_cycles = 0; wait_cycles < 10; wait_cycles = wait_cycles + 1) begin
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@(posedge m1_dst_clk); #1;
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if (m1_dst_data === 8'd0 && m1_dst_valid === 1'b0)
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dst_cleared = 1;
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end
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check(dst_cleared, "M1: dst_data=0 and dst_valid=0 after dst-only reset");
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end
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// Deassert dst_reset_n
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m1_dst_reset_n = 1;
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repeat (3) @(posedge m1_dst_clk);
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// Send new data from src, verify it arrives correctly
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m1_src_data = 8'h55;
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m1_src_valid = 1;
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@(posedge m1_src_clk); #1;
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m1_src_valid = 0;
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begin : a6_recovery
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integer wait_cycles;
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for (wait_cycles = 0; wait_cycles < 20; wait_cycles = wait_cycles + 1) begin
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@(posedge m1_dst_clk); #1;
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if (m1_dst_valid) disable a6_recovery;
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end
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end
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check(m1_dst_valid === 1'b1, "M1: dst_valid asserts after dst-only reset recovery");
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check(m1_dst_data === 8'h55, "M1: data 0x55 correct after dst-only reset recovery");
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// ── A7: Staggered Reset Deassertion ────────────────────
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$display("\n--- A7: Staggered Reset Deassertion ---");
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m1_src_reset_n = 0; m1_dst_reset_n = 0;
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m1_src_data = 0; m1_src_valid = 0;
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#100;
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// Release src_reset_n first, start sending data immediately
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m1_src_reset_n = 1;
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@(posedge m1_src_clk);
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m1_src_data = 8'hBB;
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m1_src_valid = 1;
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@(posedge m1_src_clk); #1;
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m1_src_valid = 0;
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// Wait 50ns with dst_reset_n still asserted
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#50;
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// Release dst_reset_n
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m1_dst_reset_n = 1;
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// Let sync chain clear through a few dst_clk cycles first
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repeat (5) @(posedge m1_dst_clk);
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// Src sends another value so dst can capture it fresh
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@(posedge m1_src_clk);
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m1_src_data = 8'hCC;
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m1_src_valid = 1;
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@(posedge m1_src_clk); #1;
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m1_src_valid = 0;
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begin : a7_wait
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integer wait_cycles;
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for (wait_cycles = 0; wait_cycles < 40; wait_cycles = wait_cycles + 1) begin
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@(posedge m1_dst_clk); #1;
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if (m1_dst_valid) disable a7_wait;
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end
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end
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check(m1_dst_valid === 1'b1, "M1: dst_valid asserts after staggered deassertion");
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// Accept either 0xBB (if pipeline retained) or 0xCC (if fresh capture)
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check(m1_dst_data === 8'hBB || m1_dst_data === 8'hCC,
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"M1: Data not corrupted after staggered deassertion");
|
||
|
||
// ── A8: Port Connectivity Check ────────────────────────
|
||
$display("\n--- A8: Port Connectivity Check ---");
|
||
m1_src_reset_n = 0; m1_dst_reset_n = 0;
|
||
m1_src_data = 0; m1_src_valid = 0;
|
||
#100;
|
||
m1_src_reset_n = 1; m1_dst_reset_n = 1;
|
||
repeat (5) @(posedge m1_dst_clk); #1;
|
||
|
||
// After reset deassertion, outputs should not be X or Z
|
||
check(m1_dst_data !== 8'bxxxxxxxx, "M1: dst_data is not X after reset");
|
||
check(m1_dst_data !== 8'bzzzzzzzz, "M1: dst_data is not Z after reset");
|
||
check(m1_dst_valid !== 1'bx, "M1: dst_valid is not X after reset");
|
||
check(m1_dst_valid !== 1'bz, "M1: dst_valid is not Z after reset");
|
||
|
||
// After a transfer, check again
|
||
m1_src_data = 8'h99;
|
||
m1_src_valid = 1;
|
||
@(posedge m1_src_clk); #1;
|
||
m1_src_valid = 0;
|
||
|
||
begin : a8_wait
|
||
integer wait_cycles;
|
||
for (wait_cycles = 0; wait_cycles < 20; wait_cycles = wait_cycles + 1) begin
|
||
@(posedge m1_dst_clk); #1;
|
||
if (m1_dst_valid) disable a8_wait;
|
||
end
|
||
end
|
||
check(m1_dst_data !== 8'bxxxxxxxx, "M1: dst_data is not X after transfer");
|
||
check(m1_dst_data !== 8'bzzzzzzzz, "M1: dst_data is not Z after transfer");
|
||
check(m1_dst_valid !== 1'bx, "M1: dst_valid is not X after transfer");
|
||
check(m1_dst_valid !== 1'bz, "M1: dst_valid is not Z after transfer");
|
||
|
||
// ════════════════════════════════════════════════════════
|
||
// SECTION B: cdc_single_bit tests
|
||
// ════════════════════════════════════════════════════════
|
||
$display("\n=== Section B: cdc_single_bit ===");
|
||
|
||
// ── B1: Reset behaviour ────────────────────────────────
|
||
$display("\n--- B1: Reset Behaviour ---");
|
||
m2_reset_n = 0;
|
||
m2_src_signal = 0;
|
||
#100;
|
||
check(m2_dst_signal === 1'b0, "M2: dst_signal = 0 during reset");
|
||
|
||
// ── B2: Signal propagation (low to high) ───────────────
|
||
$display("\n--- B2: Low-to-High Propagation ---");
|
||
m2_reset_n = 1;
|
||
@(posedge m2_dst_clk);
|
||
|
||
m2_src_signal = 1;
|
||
begin : b2_wait
|
||
integer wait_cycles;
|
||
reg saw_high;
|
||
saw_high = 0;
|
||
for (wait_cycles = 0; wait_cycles < 10; wait_cycles = wait_cycles + 1) begin
|
||
@(posedge m2_dst_clk); #1;
|
||
if (m2_dst_signal === 1'b1) begin
|
||
saw_high = 1;
|
||
$display(" Signal propagated after %0d dst_clk cycles", wait_cycles + 1);
|
||
disable b2_wait;
|
||
end
|
||
end
|
||
end
|
||
check(m2_dst_signal === 1'b1, "M2: 0->1 propagates through sync chain");
|
||
|
||
// ── B3: Signal propagation (high to low) ───────────────
|
||
$display("\n--- B3: High-to-Low Propagation ---");
|
||
m2_src_signal = 0;
|
||
begin : b3_wait
|
||
integer wait_cycles;
|
||
for (wait_cycles = 0; wait_cycles < 10; wait_cycles = wait_cycles + 1) begin
|
||
@(posedge m2_dst_clk); #1;
|
||
if (m2_dst_signal === 1'b0) begin
|
||
$display(" Signal de-propagated after %0d dst_clk cycles", wait_cycles + 1);
|
||
disable b3_wait;
|
||
end
|
||
end
|
||
end
|
||
check(m2_dst_signal === 1'b0, "M2: 1->0 propagates through sync chain");
|
||
|
||
// ── B4: Minimum pulse width ────────────────────────────
|
||
$display("\n--- B4: Minimum Pulse Width ---");
|
||
m2_reset_n = 0;
|
||
#100;
|
||
m2_reset_n = 1;
|
||
@(posedge m2_dst_clk);
|
||
|
||
// A single src_clk pulse may or may not be captured
|
||
// At 400:100 ratio, 1 src_clk pulse = 2.5ns, dst_clk period = 10ns
|
||
// A single src_clk pulse might be missed — that's expected behavior
|
||
m2_src_signal = 1;
|
||
@(posedge m2_src_clk); #1;
|
||
m2_src_signal = 0;
|
||
|
||
begin : b4_wait
|
||
integer wait_cycles;
|
||
reg saw_pulse;
|
||
saw_pulse = 0;
|
||
for (wait_cycles = 0; wait_cycles < 10; wait_cycles = wait_cycles + 1) begin
|
||
@(posedge m2_dst_clk); #1;
|
||
if (m2_dst_signal) saw_pulse = 1;
|
||
end
|
||
// Single src_clk pulse at 400MHz might be too short for 100MHz dst
|
||
// This is a known limitation of single-bit synchronizers
|
||
$display(" Single src_clk pulse captured: %b (may miss — expected for narrow pulse)",
|
||
saw_pulse);
|
||
check(1'b1, "M2: Narrow pulse test completed (miss is acceptable)");
|
||
end
|
||
|
||
// ── B5: Long pulse always captured ─────────────────────
|
||
$display("\n--- B5: Long Pulse Capture ---");
|
||
m2_reset_n = 0;
|
||
#100;
|
||
m2_reset_n = 1;
|
||
@(posedge m2_dst_clk);
|
||
|
||
// Pulse held for 8 src_clk cycles = 20ns (> 2× dst_clk period)
|
||
m2_src_signal = 1;
|
||
repeat (8) @(posedge m2_src_clk);
|
||
m2_src_signal = 0;
|
||
|
||
begin : b5_wait
|
||
integer wait_cycles;
|
||
reg saw_pulse;
|
||
saw_pulse = 0;
|
||
for (wait_cycles = 0; wait_cycles < 10; wait_cycles = wait_cycles + 1) begin
|
||
@(posedge m2_dst_clk); #1;
|
||
if (m2_dst_signal) saw_pulse = 1;
|
||
end
|
||
check(saw_pulse, "M2: Long pulse (8 src_clk) always captured");
|
||
end
|
||
|
||
// ── B6: Reset clears sync chain ────────────────────────
|
||
$display("\n--- B6: Reset Clears Sync Chain ---");
|
||
m2_src_signal = 1;
|
||
repeat (10) @(posedge m2_dst_clk);
|
||
// dst_signal should be 1 now
|
||
m2_reset_n = 0;
|
||
repeat (2) @(posedge m2_dst_clk); #1;
|
||
check(m2_dst_signal === 1'b0, "M2: Reset clears sync chain to 0");
|
||
m2_reset_n = 1;
|
||
m2_src_signal = 0;
|
||
|
||
// ── B7: Port Connectivity ──────────────────────────────
|
||
$display("\n--- B7: Port Connectivity ---");
|
||
m2_reset_n = 0;
|
||
m2_src_signal = 0;
|
||
#100;
|
||
m2_reset_n = 1;
|
||
repeat (5) @(posedge m2_dst_clk); #1;
|
||
|
||
check(m2_dst_signal !== 1'bx, "M2: dst_signal is not X after reset");
|
||
check(m2_dst_signal !== 1'bz, "M2: dst_signal is not Z after reset");
|
||
|
||
// Drive signal high and verify after propagation
|
||
m2_src_signal = 1;
|
||
repeat (8) @(posedge m2_dst_clk); #1;
|
||
check(m2_dst_signal !== 1'bx, "M2: dst_signal is not X after propagation");
|
||
check(m2_dst_signal !== 1'bz, "M2: dst_signal is not Z after propagation");
|
||
m2_src_signal = 0;
|
||
repeat (8) @(posedge m2_dst_clk);
|
||
|
||
// ════════════════════════════════════════════════════════
|
||
// SECTION C: cdc_handshake tests
|
||
// ════════════════════════════════════════════════════════
|
||
$display("\n=== Section C: cdc_handshake ===");
|
||
|
||
// ── C1: Reset behaviour ────────────────────────────────
|
||
$display("\n--- C1: Reset Behaviour ---");
|
||
m3_reset_n = 0;
|
||
m3_src_valid = 0;
|
||
m3_dst_ready = 0;
|
||
#200;
|
||
check(m3_src_ready === 1'b1, "M3: src_ready = 1 during reset (not busy)");
|
||
check(m3_dst_valid === 1'b0, "M3: dst_valid = 0 during reset");
|
||
|
||
// Release reset
|
||
m3_reset_n = 1;
|
||
@(posedge m3_src_clk);
|
||
|
||
// ── C2: Single data transfer ───────────────────────────
|
||
$display("\n--- C2: Single Data Transfer ---");
|
||
m3_dst_ready = 1; // destination always ready
|
||
|
||
m3_src_data = 32'hDEADBEEF;
|
||
m3_src_valid = 1;
|
||
@(posedge m3_src_clk); #1;
|
||
m3_src_valid = 0;
|
||
|
||
// Wait for data to appear at destination
|
||
begin : c2_wait
|
||
integer wait_cycles;
|
||
for (wait_cycles = 0; wait_cycles < 30; wait_cycles = wait_cycles + 1) begin
|
||
@(posedge m3_dst_clk); #1;
|
||
if (m3_dst_valid) begin
|
||
disable c2_wait;
|
||
end
|
||
end
|
||
end
|
||
check(m3_dst_valid === 1'b1, "M3: dst_valid asserts for single transfer");
|
||
check(m3_dst_data === 32'hDEADBEEF, "M3: data 0xDEADBEEF transferred correctly");
|
||
|
||
// Wait for handshake to complete (src_ready goes back to 1)
|
||
begin : c2_wait_ready
|
||
integer wait_cycles;
|
||
for (wait_cycles = 0; wait_cycles < 30; wait_cycles = wait_cycles + 1) begin
|
||
@(posedge m3_src_clk); #1;
|
||
if (m3_src_ready) disable c2_wait_ready;
|
||
end
|
||
end
|
||
check(m3_src_ready === 1'b1, "M3: src_ready reasserts after transfer");
|
||
|
||
// ── C3: Consecutive transfers ──────────────────────────
|
||
$display("\n--- C3: Consecutive Transfers ---");
|
||
m3_reset_n = 0;
|
||
#200;
|
||
m3_reset_n = 1;
|
||
@(posedge m3_src_clk);
|
||
m3_dst_ready = 1;
|
||
|
||
begin : c3_block
|
||
reg [31:0] sent_data [0:7];
|
||
reg [31:0] recv_data [0:7];
|
||
integer tx_idx, rx_idx;
|
||
integer wait_cnt;
|
||
reg all_match;
|
||
reg src_wait_done, dst_wait_done;
|
||
|
||
tx_idx = 0;
|
||
rx_idx = 0;
|
||
|
||
// Send 4 values with proper handshaking
|
||
for (tx_idx = 0; tx_idx < 4; tx_idx = tx_idx + 1) begin
|
||
sent_data[tx_idx] = (tx_idx + 1) * 32'h11111111;
|
||
|
||
// Wait for src_ready
|
||
src_wait_done = 0;
|
||
for (wait_cnt = 0; wait_cnt < 50 && !src_wait_done; wait_cnt = wait_cnt + 1) begin
|
||
@(posedge m3_src_clk); #1;
|
||
if (m3_src_ready) begin
|
||
src_wait_done = 1;
|
||
end
|
||
end
|
||
|
||
m3_src_data = sent_data[tx_idx];
|
||
m3_src_valid = 1;
|
||
@(posedge m3_src_clk); #1;
|
||
m3_src_valid = 0;
|
||
|
||
// Wait for dst_valid
|
||
dst_wait_done = 0;
|
||
for (wait_cnt = 0; wait_cnt < 50 && !dst_wait_done; wait_cnt = wait_cnt + 1) begin
|
||
@(posedge m3_dst_clk); #1;
|
||
if (m3_dst_valid) begin
|
||
recv_data[rx_idx] = m3_dst_data;
|
||
rx_idx = rx_idx + 1;
|
||
dst_wait_done = 1;
|
||
end
|
||
end
|
||
end
|
||
|
||
$display(" Consecutive: sent %0d, received %0d", tx_idx, rx_idx);
|
||
check(rx_idx == 4, "M3: All 4 consecutive transfers received");
|
||
|
||
all_match = 1;
|
||
for (i = 0; i < rx_idx && i < 4; i = i + 1) begin
|
||
if (recv_data[i] !== sent_data[i]) begin
|
||
all_match = 0;
|
||
$display(" [WARN] Consec rx[%0d]: got 0x%08x, exp 0x%08x",
|
||
i, recv_data[i], sent_data[i]);
|
||
end
|
||
end
|
||
check(all_match, "M3: All consecutive values match exactly");
|
||
end
|
||
|
||
// ── C4: Backpressure (dst_ready = 0) ───────────────────
|
||
$display("\n--- C4: Backpressure ---");
|
||
m3_reset_n = 0;
|
||
#200;
|
||
m3_reset_n = 1;
|
||
@(posedge m3_src_clk);
|
||
m3_dst_ready = 0; // NOT ready
|
||
|
||
// Send data
|
||
m3_src_data = 32'hCAFEBABE;
|
||
m3_src_valid = 1;
|
||
@(posedge m3_src_clk); #1;
|
||
m3_src_valid = 0;
|
||
|
||
// Wait — dst_valid should assert but data shouldn't be consumed
|
||
begin : c4_wait_valid
|
||
integer wait_cnt;
|
||
for (wait_cnt = 0; wait_cnt < 30; wait_cnt = wait_cnt + 1) begin
|
||
@(posedge m3_dst_clk); #1;
|
||
if (m3_dst_valid) disable c4_wait_valid;
|
||
end
|
||
end
|
||
check(m3_dst_valid === 1'b1, "M3: dst_valid asserts even without dst_ready");
|
||
check(m3_dst_data === 32'hCAFEBABE, "M3: Correct data held during backpressure");
|
||
|
||
// src should NOT be ready (busy with in-flight transfer)
|
||
check(m3_src_ready === 1'b0, "M3: src_ready = 0 during backpressure");
|
||
|
||
// Now assert dst_ready — transfer should complete
|
||
m3_dst_ready = 1;
|
||
begin : c4_wait_done
|
||
integer wait_cnt;
|
||
for (wait_cnt = 0; wait_cnt < 30; wait_cnt = wait_cnt + 1) begin
|
||
@(posedge m3_src_clk); #1;
|
||
if (m3_src_ready) disable c4_wait_done;
|
||
end
|
||
end
|
||
check(m3_src_ready === 1'b1, "M3: src_ready reasserts after backpressure release");
|
||
|
||
// ── C5: Data integrity with edge-case values ───────────
|
||
$display("\n--- C5: Edge-Case Values ---");
|
||
m3_reset_n = 0;
|
||
#200;
|
||
m3_reset_n = 1;
|
||
@(posedge m3_src_clk);
|
||
m3_dst_ready = 1;
|
||
|
||
begin : c5_block
|
||
reg [31:0] edge_vals [0:3];
|
||
reg [31:0] edge_recv [0:3];
|
||
integer tx_idx, rx_idx, wait_cnt;
|
||
reg all_match;
|
||
reg src_wait_done, dst_wait_done;
|
||
|
||
edge_vals[0] = 32'h00000000;
|
||
edge_vals[1] = 32'hFFFFFFFF;
|
||
edge_vals[2] = 32'h80000000;
|
||
edge_vals[3] = 32'h00000001;
|
||
|
||
rx_idx = 0;
|
||
|
||
for (tx_idx = 0; tx_idx < 4; tx_idx = tx_idx + 1) begin
|
||
// Wait for src_ready
|
||
src_wait_done = 0;
|
||
for (wait_cnt = 0; wait_cnt < 50 && !src_wait_done; wait_cnt = wait_cnt + 1) begin
|
||
@(posedge m3_src_clk); #1;
|
||
if (m3_src_ready) src_wait_done = 1;
|
||
end
|
||
|
||
m3_src_data = edge_vals[tx_idx];
|
||
m3_src_valid = 1;
|
||
@(posedge m3_src_clk); #1;
|
||
m3_src_valid = 0;
|
||
|
||
dst_wait_done = 0;
|
||
for (wait_cnt = 0; wait_cnt < 50 && !dst_wait_done; wait_cnt = wait_cnt + 1) begin
|
||
@(posedge m3_dst_clk); #1;
|
||
if (m3_dst_valid) begin
|
||
edge_recv[rx_idx] = m3_dst_data;
|
||
rx_idx = rx_idx + 1;
|
||
dst_wait_done = 1;
|
||
end
|
||
end
|
||
end
|
||
|
||
all_match = 1;
|
||
for (i = 0; i < 4; i = i + 1) begin
|
||
if (i < rx_idx && edge_recv[i] !== edge_vals[i]) begin
|
||
all_match = 0;
|
||
$display(" [WARN] Edge val[%0d]: got 0x%08x, exp 0x%08x",
|
||
i, edge_recv[i], edge_vals[i]);
|
||
end
|
||
end
|
||
check(rx_idx == 4, "M3: All 4 edge-case values received");
|
||
check(all_match, "M3: Edge-case values (0x0, 0xFFFF, 0x8000, 0x1) correct");
|
||
end
|
||
|
||
// ── C6: Port Connectivity + Reset Recovery ─────────────
|
||
$display("\n--- C6: Port Connectivity + Reset Recovery ---");
|
||
m3_reset_n = 0;
|
||
m3_src_valid = 0;
|
||
m3_dst_ready = 0;
|
||
#200;
|
||
m3_reset_n = 1;
|
||
repeat (5) @(posedge m3_src_clk); #1;
|
||
|
||
// Port connectivity: outputs should not be X or Z after reset
|
||
check(m3_src_ready !== 1'bx, "M3: src_ready is not X after reset");
|
||
check(m3_src_ready !== 1'bz, "M3: src_ready is not Z after reset");
|
||
check(m3_dst_valid !== 1'bx, "M3: dst_valid is not X after reset");
|
||
check(m3_dst_valid !== 1'bz, "M3: dst_valid is not Z after reset");
|
||
check(m3_dst_data !== 32'hxxxxxxxx, "M3: dst_data is not X after reset");
|
||
check(m3_dst_data !== 32'hzzzzzzzz, "M3: dst_data is not Z after reset");
|
||
|
||
// Reset during active transfer: start a transfer, then assert reset mid-flight
|
||
m3_dst_ready = 1;
|
||
|
||
// Wait for src_ready
|
||
begin : c6_wait_ready
|
||
integer wait_cnt;
|
||
for (wait_cnt = 0; wait_cnt < 30; wait_cnt = wait_cnt + 1) begin
|
||
@(posedge m3_src_clk); #1;
|
||
if (m3_src_ready) disable c6_wait_ready;
|
||
end
|
||
end
|
||
|
||
m3_src_data = 32'h12345678;
|
||
m3_src_valid = 1;
|
||
@(posedge m3_src_clk); #1;
|
||
m3_src_valid = 0;
|
||
|
||
// Wait a few cycles for transfer to be in-flight, then reset
|
||
repeat (3) @(posedge m3_dst_clk);
|
||
m3_reset_n = 0;
|
||
#200;
|
||
|
||
// Verify outputs are clean during reset
|
||
check(m3_dst_valid === 1'b0, "M3: dst_valid = 0 after mid-transfer reset");
|
||
|
||
// Release reset and verify recovery
|
||
m3_reset_n = 1;
|
||
@(posedge m3_src_clk);
|
||
m3_dst_ready = 1;
|
||
|
||
// Wait for src_ready to reassert (module recovered)
|
||
begin : c6_recovery_wait
|
||
integer wait_cnt;
|
||
reg recovered;
|
||
recovered = 0;
|
||
for (wait_cnt = 0; wait_cnt < 50; wait_cnt = wait_cnt + 1) begin
|
||
@(posedge m3_src_clk); #1;
|
||
if (m3_src_ready) begin
|
||
recovered = 1;
|
||
disable c6_recovery_wait;
|
||
end
|
||
end
|
||
check(recovered, "M3: src_ready reasserts after mid-transfer reset recovery");
|
||
end
|
||
|
||
// Verify a new transfer works after recovery
|
||
m3_src_data = 32'hABCD0000;
|
||
m3_src_valid = 1;
|
||
@(posedge m3_src_clk); #1;
|
||
m3_src_valid = 0;
|
||
|
||
begin : c6_post_reset_xfer
|
||
integer wait_cnt;
|
||
for (wait_cnt = 0; wait_cnt < 30; wait_cnt = wait_cnt + 1) begin
|
||
@(posedge m3_dst_clk); #1;
|
||
if (m3_dst_valid) disable c6_post_reset_xfer;
|
||
end
|
||
end
|
||
check(m3_dst_valid === 1'b1, "M3: dst_valid asserts for post-recovery transfer");
|
||
check(m3_dst_data === 32'hABCD0000, "M3: data 0xABCD0000 correct after reset recovery");
|
||
|
||
// ════════════════════════════════════════════════════════
|
||
// Summary
|
||
// ════════════════════════════════════════════════════════
|
||
$display("");
|
||
$display("========================================");
|
||
$display(" CDC MODULES TESTBENCH RESULTS");
|
||
$display(" PASSED: %0d / %0d", pass_count, test_num);
|
||
$display(" FAILED: %0d / %0d", fail_count, test_num);
|
||
if (fail_count == 0)
|
||
$display(" ** ALL TESTS PASSED **");
|
||
else
|
||
$display(" ** SOME TESTS FAILED **");
|
||
$display("========================================");
|
||
$display("");
|
||
|
||
#100;
|
||
$finish;
|
||
end
|
||
|
||
endmodule
|