124 lines
3.8 KiB
Verilog
124 lines
3.8 KiB
Verilog
`timescale 1ns / 1ps
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module fft_1024_forward_enhanced (
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input wire clk,
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input wire reset_n,
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input wire [15:0] data_i,
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input wire [15:0] data_q,
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input wire data_valid,
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output wire [15:0] fft_i,
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output wire [15:0] fft_q,
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output wire fft_valid
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);
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// ========== MATCH YOUR FFT IP CONFIGURATION ==========
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wire [15:0] s_axis_config_tdata; // 16-bit for your IP
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wire s_axis_config_tvalid;
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wire s_axis_config_tready;
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wire [31:0] s_axis_data_tdata; // 32-bit for your IP {Q[15:0],I[15:0]}
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wire s_axis_data_tvalid;
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wire s_axis_data_tready;
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wire s_axis_data_tlast;
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wire [31:0] m_axis_data_tdata; // 32-bit for your IP
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wire m_axis_data_tvalid;
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wire m_axis_data_tready;
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wire m_axis_data_tlast;
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// Configuration: 16-bit, bit 0 = 1 for forward FFT...
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assign s_axis_config_tdata = 16'h0001;
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assign s_axis_config_tvalid = 1'b1; // Keep valid until accepted
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assign s_axis_data_tdata = {data_q, data_i}; // {Q, I}
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assign s_axis_data_tvalid = data_valid;
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// Frame counter for tlast
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reg [9:0] sample_count;
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reg frame_active;
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n) begin
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sample_count <= 0;
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frame_active <= 0;
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end else begin
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if (data_valid && !frame_active) begin
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frame_active <= 1'b1;
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sample_count <= 0;
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end
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if (frame_active && data_valid) begin
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if (sample_count == 1023) begin
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sample_count <= 0;
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frame_active <= 0;
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end else begin
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sample_count <= sample_count + 1;
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end
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end
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end
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end
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assign s_axis_data_tlast = (sample_count == 1023) && data_valid;
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// Output: Extract from 64-bit output
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// Assuming output format is also {Q[31:0], I[31:0]}
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assign fft_i = m_axis_data_tdata[15:0]; // Lower 16 bits = I
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assign fft_q = m_axis_data_tdata[31:16]; // Upper 16 bits = Q
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assign fft_valid = m_axis_data_tvalid;
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assign m_axis_data_tready = 1'b1;
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// ========== DEBUG ==========
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/*
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reg [31:0] debug_counter = 0;
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always @(posedge clk) begin
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debug_counter <= debug_counter + 1;
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// Monitor first 2000 cycles
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if (debug_counter < 2000) begin
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// Configuration
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if (s_axis_config_tvalid && s_axis_config_tready) begin
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$display("[FFT_CORRECTED @%d] CONFIG ACCEPTED! tdata=%h",
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debug_counter, s_axis_config_tdata);
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end
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// Data input
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if (s_axis_data_tvalid && s_axis_data_tready && debug_counter < 1050) begin
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$display("[FFT_CORRECTED @%d] Data in: I=%h Q=%h count=%d tlast=%b",
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debug_counter, data_i, data_q, sample_count, s_axis_data_tlast);
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end
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// Data output
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if (m_axis_data_tvalid && debug_counter < 3000) begin
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$display("[FFT_CORRECTED @%d] FFT OUT: I=%h Q=%h",
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debug_counter, fft_i, fft_q);
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end
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// Stuck detection
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if (debug_counter == 100 && !s_axis_config_tready) begin
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$display("[FFT_CORRECTED] WARNING: config_tready still 0 after 100 cycles");
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end
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end
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end
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*/
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// ========== FFT IP INSTANCE ==========
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// This must match the name in your project
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FFT_enhanced fft_forward_inst (
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.aclk(clk),
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.aresetn(reset_n), // Active-low reset
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// Configuration (16-bit)
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.s_axis_config_tdata(s_axis_config_tdata),
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.s_axis_config_tvalid(s_axis_config_tvalid),
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.s_axis_config_tready(s_axis_config_tready),
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// Data input (64-bit)
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.s_axis_data_tdata(s_axis_data_tdata),
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.s_axis_data_tvalid(s_axis_data_tvalid),
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.s_axis_data_tready(s_axis_data_tready),
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.s_axis_data_tlast(s_axis_data_tlast),
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// Data output (64-bit)
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.m_axis_data_tdata(m_axis_data_tdata),
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.m_axis_data_tvalid(m_axis_data_tvalid),
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.m_axis_data_tlast(m_axis_data_tlast)
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);
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endmodule |