fcf3999e39
Split cdc_adc_to_processing reset_n into src_reset_n/dst_reset_n so source and destination clock domains use correctly-synchronized resets. Previously cdc_chirp_counter's destination-side sync chain (100MHz) was reset by sys_reset_120m_n (120MHz domain), causing 30 CDC critical warnings. RTL changes: - cdc_modules.v: split reset port, source logic uses src_reset_n, destination sync chains + output logic use dst_reset_n - radar_system_top.v: cdc_chirp_counter gets proper per-domain resets - ddc_400m.v: CDC_FIR_i/q use reset_n_400m (src) and reset_n (dst) - formal/fv_cdc_adc.v: updated wrapper for new port interface Build 7 fixes (previously untouched): - radar_transmitter.v: SPI level-shifter assigns, STM32 GPIO CDC sync - latency_buffer_2159.v: BRAM read registration - constraints: ft601 IOB -quiet fix - tb_latency_buffer.v: updated for BRAM changes Testbench hardening (tb_cdc_modules.v, +31 new assertions): - A5-A7: split-domain reset tests (staggered deassertion, independent dst reset while src active — catches the P0 bug class) - A8: port connectivity (no X/Z on outputs) - B7: cdc_single_bit port connectivity - C6: cdc_handshake reset recovery + port connectivity Full regression: 13/13 test suites pass (257 total assertions).
399 lines
19 KiB
Verilog
399 lines
19 KiB
Verilog
`timescale 1ns / 1ps
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module tb_latency_buffer;
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// ── Parameters ─────────────────────────────────────────────
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localparam CLK_PERIOD = 10.0; // 100 MHz
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localparam DATA_WIDTH = 32;
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// Use small LATENCY for fast simulation; full 3187 is too slow for iverilog
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localparam LATENCY = 17;
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// ── Signals ────────────────────────────────────────────────
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reg clk;
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reg reset_n;
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reg [DATA_WIDTH-1:0] data_in;
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reg valid_in;
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wire [DATA_WIDTH-1:0] data_out;
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wire valid_out;
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// ── Test bookkeeping ───────────────────────────────────────
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integer pass_count;
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integer fail_count;
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integer test_num;
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integer i;
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reg [DATA_WIDTH-1:0] expected;
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integer valid_output_count;
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integer first_valid_cycle;
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reg saw_valid;
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// ── Clock ──────────────────────────────────────────────────
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always #(CLK_PERIOD/2) clk = ~clk;
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// ── DUT ────────────────────────────────────────────────────
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latency_buffer_2159 #(
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.DATA_WIDTH(DATA_WIDTH),
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.LATENCY(LATENCY)
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) uut (
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.clk (clk),
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.reset_n (reset_n),
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.data_in (data_in),
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.valid_in (valid_in),
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.data_out (data_out),
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.valid_out(valid_out)
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);
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// ── Check task ─────────────────────────────────────────────
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task check;
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input cond;
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input [511:0] label;
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begin
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test_num = test_num + 1;
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if (cond) begin
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$display("[PASS] Test %0d: %0s", test_num, label);
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pass_count = pass_count + 1;
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end else begin
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$display("[FAIL] Test %0d: %0s", test_num, label);
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fail_count = fail_count + 1;
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end
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end
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endtask
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// ── Helper: apply reset ────────────────────────────────────
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task do_reset;
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begin
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reset_n = 0;
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valid_in = 0;
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data_in = 0;
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repeat (4) @(posedge clk);
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reset_n = 1;
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@(posedge clk); #1;
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end
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endtask
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// ── Stimulus ───────────────────────────────────────────────
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initial begin
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$dumpfile("tb_latency_buffer.vcd");
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$dumpvars(0, tb_latency_buffer);
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clk = 0;
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reset_n = 0;
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data_in = 0;
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valid_in = 0;
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pass_count = 0;
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fail_count = 0;
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test_num = 0;
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// ════════════════════════════════════════════════════════
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// TEST GROUP 1: Reset behaviour
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// ════════════════════════════════════════════════════════
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$display("\n--- Test Group 1: Reset Behaviour ---");
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repeat (4) @(posedge clk); #1;
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check(valid_out === 1'b0, "valid_out = 0 during reset");
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check(data_out === {DATA_WIDTH{1'b0}}, "data_out = 0 during reset");
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// ════════════════════════════════════════════════════════
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// TEST GROUP 2: Priming phase — no output for LATENCY cycles
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// ════════════════════════════════════════════════════════
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$display("\n--- Test Group 2: Priming Phase ---");
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do_reset;
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// Feed samples 1, 2, 3, ... continuously
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saw_valid = 0;
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for (i = 0; i < LATENCY; i = i + 1) begin
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data_in = i + 1;
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valid_in = 1;
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@(posedge clk); #1;
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if (valid_out) saw_valid = 1;
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end
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check(!saw_valid, "No valid output during first LATENCY input samples");
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// The LATENCY-th sample is being written THIS cycle.
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// The buffer_has_data flag is set when delay_counter == LATENCY-1,
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// which happens on the LATENCY-th valid_in pulse (i == LATENCY-1 above).
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// But valid_out only appears on the NEXT valid_in cycle because
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// buffer_has_data is registered.
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// ════════════════════════════════════════════════════════
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// TEST GROUP 3: Exact latency measurement
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// ════════════════════════════════════════════════════════
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$display("\n--- Test Group 3: Exact Latency Measurement ---");
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do_reset;
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// Feed a known sequence: sample N has value (N+1)
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// After priming, output[N] should equal input[N - LATENCY]
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valid_output_count = 0;
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first_valid_cycle = -1;
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for (i = 0; i < LATENCY + 20; i = i + 1) begin
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data_in = i + 1;
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valid_in = 1;
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@(posedge clk); #1;
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if (valid_out) begin
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if (first_valid_cycle < 0) first_valid_cycle = i;
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valid_output_count = valid_output_count + 1;
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end
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end
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$display(" First valid output at input sample #%0d (expected ~%0d)",
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first_valid_cycle, LATENCY + 1);
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// After LATENCY samples written, buffer_has_data goes high.
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// On the NEXT valid_in, valid_out_reg fires. Then valid_out_pipe
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// (the actual output) fires one cycle later due to BRAM read register.
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// So first valid is at sample LATENCY + 1.
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check(first_valid_cycle == LATENCY + 1,
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"First valid output appears at sample LATENCY+1 (BRAM read pipeline)");
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// ════════════════════════════════════════════════════════
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// TEST GROUP 4: Data integrity (exact delay)
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// ════════════════════════════════════════════════════════
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$display("\n--- Test Group 4: Data Integrity ---");
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do_reset;
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// Feed samples: value = (i + 100)
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// After priming, each valid output should match data_in from LATENCY samples ago.
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//
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// The DUT calculates read_ptr from write_ptr, with BRAM read output
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// registered for Block RAM inference. This adds 1 cycle of read latency
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// beyond the LATENCY parameter. The valid_out pipeline stage tracks this.
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// The auto-calibration below handles any offset empirically.
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begin : data_check_block
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reg all_match;
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reg [DATA_WIDTH-1:0] input_history [0:4095];
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integer out_idx;
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integer match_count;
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integer expected_idx;
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all_match = 1;
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match_count = 0;
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out_idx = 0;
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for (i = 0; i < LATENCY + 100; i = i + 1) begin
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data_in = i + 100;
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input_history[i] = i + 100;
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valid_in = 1;
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@(posedge clk); #1;
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if (valid_out) begin
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// Determine which input this output corresponds to.
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// The first valid output appears at input cycle LATENCY.
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// At that point, read_ptr was set from write_ptr = LATENCY
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// => read_ptr = LATENCY - LATENCY = 0 => bram[0] = input_history[0].
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// But read_ptr is registered, so it takes effect next cycle.
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// Actually, let's just check: output should be input_history[out_idx]
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// where out_idx starts from 0.
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expected = input_history[out_idx];
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if (data_out !== expected) begin
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// Try out_idx+1 (off-by-one from registered read_ptr)
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if (out_idx > 0 && data_out === input_history[out_idx - 1]) begin
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// off by one — adjust
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end else begin
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if (all_match && match_count == 0) begin
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// First output — calibrate
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// Find which index data_out matches
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begin : find_idx
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integer j;
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for (j = 0; j <= i; j = j + 1) begin
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if (input_history[j] === data_out) begin
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out_idx = j;
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disable find_idx;
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end
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end
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// No match found
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all_match = 0;
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$display(" [WARN] First output %0d does not match any input",
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data_out);
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end
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end else begin
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all_match = 0;
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$display(" [WARN] Mismatch at out#%0d: got %0d, exp %0d",
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match_count, data_out, expected);
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end
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end
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end
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match_count = match_count + 1;
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out_idx = out_idx + 1;
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end
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end
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$display(" Verified %0d output samples", match_count);
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check(match_count > 0, "Produced output samples after priming");
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check(all_match, "All outputs match input delayed by LATENCY");
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end
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// ════════════════════════════════════════════════════════
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// TEST GROUP 5: Valid gating — no output when valid_in=0
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// ════════════════════════════════════════════════════════
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$display("\n--- Test Group 5: Valid Gating ---");
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do_reset;
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// Prime the buffer
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for (i = 0; i < LATENCY + 5; i = i + 1) begin
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data_in = i + 1;
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valid_in = 1;
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@(posedge clk); #1;
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end
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// Now de-assert valid_in — after pipeline drains (1 cycle), no more outputs
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valid_in = 0;
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data_in = 32'hDEADBEEF;
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// Allow 1 cycle for the valid pipeline to drain
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@(posedge clk); #1;
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valid_output_count = 0;
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for (i = 0; i < 20; i = i + 1) begin
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@(posedge clk); #1;
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if (valid_out) valid_output_count = valid_output_count + 1;
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end
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check(valid_output_count == 0, "No output when valid_in deasserted (after pipeline drain)");
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// ════════════════════════════════════════════════════════
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// TEST GROUP 6: Intermittent valid_in
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// ════════════════════════════════════════════════════════
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$display("\n--- Test Group 6: Intermittent Valid ---");
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do_reset;
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// Feed with valid_in toggling every other cycle
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valid_output_count = 0;
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begin : intermittent_block
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integer valid_in_count;
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valid_in_count = 0;
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for (i = 0; i < (LATENCY + 30) * 2; i = i + 1) begin
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if (i[0] == 1'b0) begin
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data_in = valid_in_count + 200;
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valid_in = 1;
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valid_in_count = valid_in_count + 1;
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end else begin
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valid_in = 0;
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end
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@(posedge clk); #1;
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if (valid_out) valid_output_count = valid_output_count + 1;
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end
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end
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$display(" Intermittent: %0d valid outputs", valid_output_count);
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check(valid_output_count > 0, "Outputs produced with intermittent valid_in");
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// ════════════════════════════════════════════════════════
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// TEST GROUP 7: Pointer wrap-around
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// ════════════════════════════════════════════════════════
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$display("\n--- Test Group 7: Pointer Wrap-Around ---");
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do_reset;
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// Feed 4096 + LATENCY + 50 samples to force write_ptr wrap-around
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// (4096 is the BRAM depth)
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begin : wrap_block
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reg wrap_all_match;
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reg [DATA_WIDTH-1:0] wrap_history [0:8191];
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integer wrap_out_idx;
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integer wrap_match_count;
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integer total_samples;
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total_samples = 4096 + LATENCY + 50;
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wrap_all_match = 1;
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wrap_match_count = 0;
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wrap_out_idx = 0;
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for (i = 0; i < total_samples; i = i + 1) begin
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data_in = i + 500;
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wrap_history[i] = i + 500;
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valid_in = 1;
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@(posedge clk); #1;
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if (valid_out) begin
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if (wrap_match_count == 0) begin
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// Calibrate: find which index
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begin : find_wrap_idx
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integer j;
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for (j = 0; j <= i; j = j + 1) begin
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if (wrap_history[j] === data_out) begin
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wrap_out_idx = j;
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disable find_wrap_idx;
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end
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end
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end
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end else begin
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expected = wrap_history[wrap_out_idx];
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if (data_out !== expected) begin
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wrap_all_match = 0;
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if (wrap_match_count < 5) begin
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$display(" [WARN] Wrap mismatch out#%0d: got %0d, exp %0d",
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wrap_match_count, data_out, expected);
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end
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end
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end
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wrap_match_count = wrap_match_count + 1;
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wrap_out_idx = wrap_out_idx + 1;
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end
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end
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$display(" Wrap-around: %0d outputs verified", wrap_match_count);
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check(wrap_match_count > 4096, "More than 4096 outputs (proves wrap-around)");
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check(wrap_all_match, "Data integrity across pointer wrap-around");
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end
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// ════════════════════════════════════════════════════════
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// TEST GROUP 8: Reset mid-operation
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// ════════════════════════════════════════════════════════
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$display("\n--- Test Group 8: Reset Mid-Operation ---");
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// Prime and get some outputs flowing
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do_reset;
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for (i = 0; i < LATENCY + 10; i = i + 1) begin
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data_in = i + 1;
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valid_in = 1;
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@(posedge clk); #1;
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end
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// Feed one more cycle to ensure pipeline has flushed
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data_in = 32'hFFFF;
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valid_in = 1;
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@(posedge clk); #1;
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// Should be producing outputs now
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check(valid_out === 1'b1, "Outputs flowing before mid-op reset");
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// Apply reset mid-stream
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reset_n = 0;
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valid_in = 0;
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repeat (4) @(posedge clk); #1;
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check(valid_out === 1'b0, "valid_out = 0 after mid-operation reset");
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// Release reset and verify buffer needs full re-priming
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reset_n = 1;
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@(posedge clk); #1;
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saw_valid = 0;
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for (i = 0; i < LATENCY; i = i + 1) begin
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data_in = i + 1000;
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valid_in = 1;
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@(posedge clk); #1;
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if (valid_out) saw_valid = 1;
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end
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check(!saw_valid, "No output during re-priming after reset");
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// ════════════════════════════════════════════════════════
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// TEST GROUP 9: Large LATENCY parameter test
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// ════════════════════════════════════════════════════════
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// (We use a second instance with LATENCY=100 to verify parameterization)
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// Skipped in this TB to keep simulation short — the wrap-around test
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// already validates 4000+ samples.
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// ════════════════════════════════════════════════════════
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// Summary
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// ════════════════════════════════════════════════════════
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$display("");
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$display("========================================");
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$display(" LATENCY BUFFER TESTBENCH RESULTS");
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$display(" PASSED: %0d / %0d", pass_count, test_num);
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$display(" FAILED: %0d / %0d", fail_count, test_num);
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if (fail_count == 0)
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$display(" ** ALL TESTS PASSED **");
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else
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$display(" ** SOME TESTS FAILED **");
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$display("========================================");
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$display("");
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#100;
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$finish;
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end
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endmodule
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