c983a3c705
Phase 0+ timing optimization (attempts #13-22 + implementation): NCO (nco_400m_enhanced.v): - 4-stage pipeline: DSP48E1 accumulate -> LUT read -> negate -> quadrant MUX - DSP48E1 phase accumulator in P=P+C mode (eliminates 8-stage CARRY4 chain) - Registered phase_inc_dithered to break cascaded 32-bit add path DDC (ddc_400m.v): - Direct DSP48E1 instantiation for I/Q mixers (AREG=1, BREG=1, MREG=1, PREG=1) - CEP=1, RSTP=!reset_n for proper pipeline control - 3-stage dsp_valid_pipe for PREG=1 latency - Behavioral sim model under ifdef SIMULATION for Icarus compatibility CIC (cic_decimator_4x_enhanced.v): - 28-bit accumulators (was 36) per CIC width formula: 18 + 5*log2(4) = 28 - Removed integrator/comb saturation (CIC uses wrapping arithmetic by design) - Pipelined output saturation comparison CDC/ASYNC_REG: - ASYNC_REG attribute on all CDC synchronizer registers (cdc_modules.v, radar_system_top.v, usb_data_interface.v) - Sync reset in generate blocks (cdc_modules.v) Results: Vivado post-implementation WNS=+1.196ns, 0 failing endpoints, 850 LUTs (1.34%), 466 FFs (0.37%), 2 DSP48E1 (0.83%) on xc7a100t. All testbenches pass: 241/244 (3 known stub failures).
678 B
678 B
| 1 | input_sample | output_sample | data_out | data_out_valid |
|---|---|---|---|---|
| 2 | 6 | 0 | 0 | 1 |
| 3 | 10 | 1 | 0 | 1 |
| 4 | 14 | 2 | 0 | 1 |
| 5 | 18 | 3 | 0 | 1 |
| 6 | 22 | 4 | 0 | 1 |
| 7 | 26 | 5 | 0 | 1 |
| 8 | 30 | 6 | 0 | 1 |
| 9 | 34 | 7 | 118 | 1 |
| 10 | 38 | 8 | 651 | 1 |
| 11 | 42 | 9 | 979 | 1 |
| 12 | 46 | 10 | 1000 | 1 |
| 13 | 50 | 11 | 1000 | 1 |
| 14 | 54 | 12 | 1000 | 1 |
| 15 | 58 | 13 | 1000 | 1 |
| 16 | 62 | 14 | 1000 | 1 |
| 17 | 66 | 15 | 1000 | 1 |
| 18 | 70 | 16 | 1000 | 1 |
| 19 | 74 | 17 | 1000 | 1 |
| 20 | 78 | 18 | 1000 | 1 |
| 21 | 82 | 19 | 1000 | 1 |
| 22 | 86 | 20 | 1000 | 1 |
| 23 | 90 | 21 | 1000 | 1 |
| 24 | 94 | 22 | 1000 | 1 |
| 25 | 98 | 23 | 1000 | 1 |
| 26 | 102 | 24 | 1000 | 1 |
| 27 | 106 | 25 | 1000 | 1 |
| 28 | 110 | 26 | 1000 | 1 |
| 29 | 114 | 27 | 1000 | 1 |
| 30 | 118 | 28 | 1000 | 1 |
| 31 | 122 | 29 | 1000 | 1 |
| 32 | 126 | 30 | 1000 | 1 |
| 33 | 130 | 31 | 1000 | 1 |
| 34 | 134 | 32 | 1000 | 1 |
| 35 | 138 | 33 | 1000 | 1 |
| 36 | 142 | 34 | 1000 | 1 |
| 37 | 146 | 35 | 1000 | 1 |
| 38 | 150 | 36 | 1000 | 1 |
| 39 | 154 | 37 | 1000 | 1 |
| 40 | 158 | 38 | 1000 | 1 |
| 41 | 162 | 39 | 1000 | 1 |
| 42 | 166 | 40 | 1000 | 1 |
| 43 | 170 | 41 | 1000 | 1 |
| 44 | 174 | 42 | 1000 | 1 |
| 45 | 178 | 43 | 1000 | 1 |
| 46 | 182 | 44 | 1000 | 1 |
| 47 | 186 | 45 | 1000 | 1 |
| 48 | 190 | 46 | 1000 | 1 |
| 49 | 194 | 47 | 1000 | 1 |
| 50 | 198 | 48 | 1000 | 1 |