b823d83feb
New testbenches: - tb_latency_buffer.v: 13/13 tests for BRAM delay line (P1-3) - tb_cdc_modules.v: 27/27 tests for all 3 CDC primitives (P1-4) - tb_ad9484_xsim.v: XSim testbench for AD9484 with Xilinx BUFIO/IDDR - tb_nco_xsim.v: XSim testbench for NCO DSP48E1 path verification Fixes: - tb_usb_data_interface.v: updated test 33 from divide-by-2 check to ODDR-style clock forwarding verification (39/39 pass) - rx_final_doppler_out.csv: updated golden reference after bug fixes
627 lines
25 KiB
Verilog
627 lines
25 KiB
Verilog
`timescale 1ns / 1ps
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module tb_cdc_modules;
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// ── Clock periods (reflecting real system) ─────────────────
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localparam SRC_CLK_PERIOD = 2.5; // 400 MHz (ADC domain)
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localparam DST_CLK_PERIOD = 10.0; // 100 MHz (processing domain)
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// For handshake tests, use different ratio
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localparam HS_SRC_PERIOD = 10.0; // 100 MHz
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localparam HS_DST_PERIOD = 7.0; // ~143 MHz (non-integer ratio)
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// ── Test bookkeeping ───────────────────────────────────────
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integer pass_count;
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integer fail_count;
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integer test_num;
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integer i;
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// ── Check task ─────────────────────────────────────────────
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task check;
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input cond;
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input [511:0] label;
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begin
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test_num = test_num + 1;
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if (cond) begin
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$display("[PASS] Test %0d: %0s", test_num, label);
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pass_count = pass_count + 1;
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end else begin
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$display("[FAIL] Test %0d: %0s", test_num, label);
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fail_count = fail_count + 1;
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end
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end
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endtask
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// ════════════════════════════════════════════════════════════
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// MODULE 1: cdc_adc_to_processing (Gray-code multi-bit CDC)
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// ════════════════════════════════════════════════════════════
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reg m1_src_clk;
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reg m1_dst_clk;
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reg m1_reset_n;
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reg [7:0] m1_src_data;
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reg m1_src_valid;
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wire [7:0] m1_dst_data;
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wire m1_dst_valid;
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always #(SRC_CLK_PERIOD/2) m1_src_clk = ~m1_src_clk;
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always #(DST_CLK_PERIOD/2) m1_dst_clk = ~m1_dst_clk;
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cdc_adc_to_processing #(
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.WIDTH(8),
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.STAGES(3)
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) uut_m1 (
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.src_clk (m1_src_clk),
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.dst_clk (m1_dst_clk),
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.reset_n (m1_reset_n),
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.src_data (m1_src_data),
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.src_valid(m1_src_valid),
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.dst_data (m1_dst_data),
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.dst_valid(m1_dst_valid)
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);
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// ════════════════════════════════════════════════════════════
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// MODULE 2: cdc_single_bit
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// ════════════════════════════════════════════════════════════
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reg m2_src_clk;
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reg m2_dst_clk;
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reg m2_reset_n;
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reg m2_src_signal;
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wire m2_dst_signal;
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always #(SRC_CLK_PERIOD/2) m2_src_clk = ~m2_src_clk;
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always #(DST_CLK_PERIOD/2) m2_dst_clk = ~m2_dst_clk;
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cdc_single_bit #(
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.STAGES(3)
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) uut_m2 (
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.src_clk (m2_src_clk),
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.dst_clk (m2_dst_clk),
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.reset_n (m2_reset_n),
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.src_signal(m2_src_signal),
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.dst_signal(m2_dst_signal)
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);
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// ════════════════════════════════════════════════════════════
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// MODULE 3: cdc_handshake
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// ════════════════════════════════════════════════════════════
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reg m3_src_clk;
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reg m3_dst_clk;
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reg m3_reset_n;
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reg [31:0] m3_src_data;
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reg m3_src_valid;
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wire m3_src_ready;
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wire [31:0] m3_dst_data;
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wire m3_dst_valid;
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reg m3_dst_ready;
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always #(HS_SRC_PERIOD/2) m3_src_clk = ~m3_src_clk;
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always #(HS_DST_PERIOD/2) m3_dst_clk = ~m3_dst_clk;
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cdc_handshake #(
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.WIDTH(32)
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) uut_m3 (
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.src_clk (m3_src_clk),
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.dst_clk (m3_dst_clk),
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.reset_n (m3_reset_n),
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.src_data (m3_src_data),
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.src_valid(m3_src_valid),
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.src_ready(m3_src_ready),
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.dst_data (m3_dst_data),
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.dst_valid(m3_dst_valid),
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.dst_ready(m3_dst_ready)
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);
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// ── Main test sequence ─────────────────────────────────────
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initial begin
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$dumpfile("tb_cdc_modules.vcd");
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$dumpvars(0, tb_cdc_modules);
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// Init all clocks and signals
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m1_src_clk = 0; m1_dst_clk = 0; m1_reset_n = 0;
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m1_src_data = 0; m1_src_valid = 0;
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m2_src_clk = 0; m2_dst_clk = 0; m2_reset_n = 0;
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m2_src_signal = 0;
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m3_src_clk = 0; m3_dst_clk = 0; m3_reset_n = 0;
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m3_src_data = 0; m3_src_valid = 0; m3_dst_ready = 0;
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pass_count = 0; fail_count = 0; test_num = 0;
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// ════════════════════════════════════════════════════════
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// SECTION A: cdc_adc_to_processing tests
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// ════════════════════════════════════════════════════════
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$display("\n=== Section A: cdc_adc_to_processing (Gray-code CDC) ===");
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// ── A1: Reset behaviour ────────────────────────────────
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$display("\n--- A1: Reset Behaviour ---");
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m1_reset_n = 0;
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#100; // let both clocks run
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check(m1_dst_valid === 1'b0, "M1: dst_valid = 0 during reset");
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check(m1_dst_data === 8'd0, "M1: dst_data = 0 during reset");
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// Release reset
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@(posedge m1_dst_clk);
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m1_reset_n = 1;
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@(posedge m1_src_clk);
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// ── A2: Single value transfer ──────────────────────────
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$display("\n--- A2: Single Value Transfer ---");
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m1_src_data = 8'hA5;
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m1_src_valid = 1;
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@(posedge m1_src_clk); #1;
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m1_src_valid = 0;
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// Wait for CDC propagation (3 stages × dst_clk + margin)
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begin : a2_wait
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integer wait_cycles;
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reg saw_valid;
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saw_valid = 0;
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for (wait_cycles = 0; wait_cycles < 20; wait_cycles = wait_cycles + 1) begin
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@(posedge m1_dst_clk); #1;
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if (m1_dst_valid) begin
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saw_valid = 1;
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disable a2_wait;
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end
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end
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end
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check(m1_dst_valid === 1'b1, "M1: dst_valid asserts after CDC");
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check(m1_dst_data === 8'hA5, "M1: data 0xA5 transferred correctly");
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// ── A3: Multiple sequential values ─────────────────────
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$display("\n--- A3: Multiple Sequential Values ---");
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m1_reset_n = 0;
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#100;
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m1_reset_n = 1;
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@(posedge m1_src_clk);
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begin : a3_block
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reg [7:0] received_values [0:31];
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integer rx_count;
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integer tx_count;
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integer total_wait;
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reg all_received;
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rx_count = 0;
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// Send 8 values, one per src_clk cycle
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// At 400:100 ratio, src sends 4x faster than dst can sample
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// Gray-code CDC may miss intermediate values — that's expected.
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// What matters is that received values are VALID (not corrupted).
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for (tx_count = 0; tx_count < 8; tx_count = tx_count + 1) begin
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m1_src_data = tx_count * 37 + 10; // 10, 47, 84, 121, 158, 195, 232, 13
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m1_src_valid = 1;
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@(posedge m1_src_clk); #1;
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end
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m1_src_valid = 0;
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// Collect outputs
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for (total_wait = 0; total_wait < 40; total_wait = total_wait + 1) begin
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@(posedge m1_dst_clk); #1;
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if (m1_dst_valid) begin
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received_values[rx_count] = m1_dst_data;
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rx_count = rx_count + 1;
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end
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end
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$display(" Sent 8 values at 400MHz, received %0d valid values at 100MHz",
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rx_count);
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check(rx_count > 0, "M1: At least one value received from burst");
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// Verify last received value matches last sent value
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// (The CDC should eventually stabilize to the last written value)
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if (rx_count > 0) begin
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// Check that every received value is one of the sent values
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begin : verify_received
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reg [7:0] sent_vals [0:7];
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reg found;
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integer j, k;
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reg all_valid;
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for (j = 0; j < 8; j = j + 1) begin
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sent_vals[j] = j * 37 + 10;
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end
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all_valid = 1;
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for (j = 0; j < rx_count; j = j + 1) begin
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found = 0;
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for (k = 0; k < 8; k = k + 1) begin
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if (received_values[j] === sent_vals[k]) found = 1;
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end
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if (!found) begin
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all_valid = 0;
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$display(" [WARN] Received value 0x%02x not in sent set",
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received_values[j]);
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end
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end
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check(all_valid, "M1: All received values are valid (no corruption)");
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end
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end else begin
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check(1'b0, "M1: All received values are valid (no corruption)");
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end
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end
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// ── A4: Slow sender (one value every 4 dst_clk cycles) ─
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$display("\n--- A4: Slow Sender ---");
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m1_reset_n = 0;
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#100;
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m1_reset_n = 1;
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@(posedge m1_src_clk);
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begin : a4_block
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reg [7:0] expected_vals [0:7];
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reg [7:0] got_vals [0:7];
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integer tx_idx, rx_idx, wait_cnt;
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reg all_match;
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rx_idx = 0;
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for (tx_idx = 0; tx_idx < 4; tx_idx = tx_idx + 1) begin
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expected_vals[tx_idx] = (tx_idx + 1) * 50; // 50, 100, 150, 200
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m1_src_data = expected_vals[tx_idx];
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m1_src_valid = 1;
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@(posedge m1_src_clk); #1;
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m1_src_valid = 0;
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// Wait long enough for CDC to propagate
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for (wait_cnt = 0; wait_cnt < 15; wait_cnt = wait_cnt + 1) begin
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@(posedge m1_dst_clk); #1;
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if (m1_dst_valid && rx_idx < 8) begin
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got_vals[rx_idx] = m1_dst_data;
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rx_idx = rx_idx + 1;
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end
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end
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end
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$display(" Slow send: sent 4, received %0d", rx_idx);
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check(rx_idx == 4, "M1: All 4 slow-sent values received");
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all_match = 1;
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for (i = 0; i < rx_idx && i < 4; i = i + 1) begin
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if (got_vals[i] !== expected_vals[i]) begin
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all_match = 0;
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$display(" [WARN] Slow rx[%0d]: got 0x%02x, exp 0x%02x",
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i, got_vals[i], expected_vals[i]);
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end
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end
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check(all_match, "M1: Slow-sent values match exactly");
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end
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// ════════════════════════════════════════════════════════
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// SECTION B: cdc_single_bit tests
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// ════════════════════════════════════════════════════════
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$display("\n=== Section B: cdc_single_bit ===");
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// ── B1: Reset behaviour ────────────────────────────────
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$display("\n--- B1: Reset Behaviour ---");
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m2_reset_n = 0;
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m2_src_signal = 0;
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#100;
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check(m2_dst_signal === 1'b0, "M2: dst_signal = 0 during reset");
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// ── B2: Signal propagation (low to high) ───────────────
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$display("\n--- B2: Low-to-High Propagation ---");
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m2_reset_n = 1;
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@(posedge m2_dst_clk);
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m2_src_signal = 1;
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begin : b2_wait
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integer wait_cycles;
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reg saw_high;
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saw_high = 0;
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for (wait_cycles = 0; wait_cycles < 10; wait_cycles = wait_cycles + 1) begin
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@(posedge m2_dst_clk); #1;
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if (m2_dst_signal === 1'b1) begin
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saw_high = 1;
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$display(" Signal propagated after %0d dst_clk cycles", wait_cycles + 1);
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disable b2_wait;
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end
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end
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end
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check(m2_dst_signal === 1'b1, "M2: 0->1 propagates through sync chain");
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// ── B3: Signal propagation (high to low) ───────────────
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$display("\n--- B3: High-to-Low Propagation ---");
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m2_src_signal = 0;
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begin : b3_wait
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integer wait_cycles;
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for (wait_cycles = 0; wait_cycles < 10; wait_cycles = wait_cycles + 1) begin
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@(posedge m2_dst_clk); #1;
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if (m2_dst_signal === 1'b0) begin
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$display(" Signal de-propagated after %0d dst_clk cycles", wait_cycles + 1);
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disable b3_wait;
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end
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end
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end
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check(m2_dst_signal === 1'b0, "M2: 1->0 propagates through sync chain");
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// ── B4: Minimum pulse width ────────────────────────────
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$display("\n--- B4: Minimum Pulse Width ---");
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m2_reset_n = 0;
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#100;
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m2_reset_n = 1;
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@(posedge m2_dst_clk);
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// A single src_clk pulse may or may not be captured
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// At 400:100 ratio, 1 src_clk pulse = 2.5ns, dst_clk period = 10ns
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// A single src_clk pulse might be missed — that's expected behavior
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m2_src_signal = 1;
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@(posedge m2_src_clk); #1;
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m2_src_signal = 0;
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begin : b4_wait
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integer wait_cycles;
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reg saw_pulse;
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saw_pulse = 0;
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for (wait_cycles = 0; wait_cycles < 10; wait_cycles = wait_cycles + 1) begin
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@(posedge m2_dst_clk); #1;
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if (m2_dst_signal) saw_pulse = 1;
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end
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// Single src_clk pulse at 400MHz might be too short for 100MHz dst
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// This is a known limitation of single-bit synchronizers
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$display(" Single src_clk pulse captured: %b (may miss — expected for narrow pulse)",
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saw_pulse);
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check(1'b1, "M2: Narrow pulse test completed (miss is acceptable)");
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end
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// ── B5: Long pulse always captured ─────────────────────
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$display("\n--- B5: Long Pulse Capture ---");
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m2_reset_n = 0;
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#100;
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m2_reset_n = 1;
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@(posedge m2_dst_clk);
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// Pulse held for 8 src_clk cycles = 20ns (> 2× dst_clk period)
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m2_src_signal = 1;
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repeat (8) @(posedge m2_src_clk);
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m2_src_signal = 0;
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begin : b5_wait
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integer wait_cycles;
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reg saw_pulse;
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saw_pulse = 0;
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for (wait_cycles = 0; wait_cycles < 10; wait_cycles = wait_cycles + 1) begin
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@(posedge m2_dst_clk); #1;
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if (m2_dst_signal) saw_pulse = 1;
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end
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check(saw_pulse, "M2: Long pulse (8 src_clk) always captured");
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end
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// ── B6: Reset clears sync chain ────────────────────────
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$display("\n--- B6: Reset Clears Sync Chain ---");
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m2_src_signal = 1;
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repeat (10) @(posedge m2_dst_clk);
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// dst_signal should be 1 now
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m2_reset_n = 0;
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repeat (2) @(posedge m2_dst_clk); #1;
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check(m2_dst_signal === 1'b0, "M2: Reset clears sync chain to 0");
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m2_reset_n = 1;
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m2_src_signal = 0;
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// ════════════════════════════════════════════════════════
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// SECTION C: cdc_handshake tests
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// ════════════════════════════════════════════════════════
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$display("\n=== Section C: cdc_handshake ===");
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// ── C1: Reset behaviour ────────────────────────────────
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$display("\n--- C1: Reset Behaviour ---");
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m3_reset_n = 0;
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m3_src_valid = 0;
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m3_dst_ready = 0;
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#200;
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check(m3_src_ready === 1'b1, "M3: src_ready = 1 during reset (not busy)");
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check(m3_dst_valid === 1'b0, "M3: dst_valid = 0 during reset");
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// Release reset
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m3_reset_n = 1;
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@(posedge m3_src_clk);
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// ── C2: Single data transfer ───────────────────────────
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$display("\n--- C2: Single Data Transfer ---");
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m3_dst_ready = 1; // destination always ready
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m3_src_data = 32'hDEADBEEF;
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m3_src_valid = 1;
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@(posedge m3_src_clk); #1;
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m3_src_valid = 0;
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// Wait for data to appear at destination
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begin : c2_wait
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integer wait_cycles;
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for (wait_cycles = 0; wait_cycles < 30; wait_cycles = wait_cycles + 1) begin
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@(posedge m3_dst_clk); #1;
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if (m3_dst_valid) begin
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disable c2_wait;
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end
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end
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end
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check(m3_dst_valid === 1'b1, "M3: dst_valid asserts for single transfer");
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check(m3_dst_data === 32'hDEADBEEF, "M3: data 0xDEADBEEF transferred correctly");
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// Wait for handshake to complete (src_ready goes back to 1)
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begin : c2_wait_ready
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integer wait_cycles;
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for (wait_cycles = 0; wait_cycles < 30; wait_cycles = wait_cycles + 1) begin
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@(posedge m3_src_clk); #1;
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if (m3_src_ready) disable c2_wait_ready;
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end
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end
|
||
check(m3_src_ready === 1'b1, "M3: src_ready reasserts after transfer");
|
||
|
||
// ── C3: Consecutive transfers ──────────────────────────
|
||
$display("\n--- C3: Consecutive Transfers ---");
|
||
m3_reset_n = 0;
|
||
#200;
|
||
m3_reset_n = 1;
|
||
@(posedge m3_src_clk);
|
||
m3_dst_ready = 1;
|
||
|
||
begin : c3_block
|
||
reg [31:0] sent_data [0:7];
|
||
reg [31:0] recv_data [0:7];
|
||
integer tx_idx, rx_idx;
|
||
integer wait_cnt;
|
||
reg all_match;
|
||
reg src_wait_done, dst_wait_done;
|
||
|
||
tx_idx = 0;
|
||
rx_idx = 0;
|
||
|
||
// Send 4 values with proper handshaking
|
||
for (tx_idx = 0; tx_idx < 4; tx_idx = tx_idx + 1) begin
|
||
sent_data[tx_idx] = (tx_idx + 1) * 32'h11111111;
|
||
|
||
// Wait for src_ready
|
||
src_wait_done = 0;
|
||
for (wait_cnt = 0; wait_cnt < 50 && !src_wait_done; wait_cnt = wait_cnt + 1) begin
|
||
@(posedge m3_src_clk); #1;
|
||
if (m3_src_ready) begin
|
||
src_wait_done = 1;
|
||
end
|
||
end
|
||
|
||
m3_src_data = sent_data[tx_idx];
|
||
m3_src_valid = 1;
|
||
@(posedge m3_src_clk); #1;
|
||
m3_src_valid = 0;
|
||
|
||
// Wait for dst_valid
|
||
dst_wait_done = 0;
|
||
for (wait_cnt = 0; wait_cnt < 50 && !dst_wait_done; wait_cnt = wait_cnt + 1) begin
|
||
@(posedge m3_dst_clk); #1;
|
||
if (m3_dst_valid) begin
|
||
recv_data[rx_idx] = m3_dst_data;
|
||
rx_idx = rx_idx + 1;
|
||
dst_wait_done = 1;
|
||
end
|
||
end
|
||
end
|
||
|
||
$display(" Consecutive: sent %0d, received %0d", tx_idx, rx_idx);
|
||
check(rx_idx == 4, "M3: All 4 consecutive transfers received");
|
||
|
||
all_match = 1;
|
||
for (i = 0; i < rx_idx && i < 4; i = i + 1) begin
|
||
if (recv_data[i] !== sent_data[i]) begin
|
||
all_match = 0;
|
||
$display(" [WARN] Consec rx[%0d]: got 0x%08x, exp 0x%08x",
|
||
i, recv_data[i], sent_data[i]);
|
||
end
|
||
end
|
||
check(all_match, "M3: All consecutive values match exactly");
|
||
end
|
||
|
||
// ── C4: Backpressure (dst_ready = 0) ───────────────────
|
||
$display("\n--- C4: Backpressure ---");
|
||
m3_reset_n = 0;
|
||
#200;
|
||
m3_reset_n = 1;
|
||
@(posedge m3_src_clk);
|
||
m3_dst_ready = 0; // NOT ready
|
||
|
||
// Send data
|
||
m3_src_data = 32'hCAFEBABE;
|
||
m3_src_valid = 1;
|
||
@(posedge m3_src_clk); #1;
|
||
m3_src_valid = 0;
|
||
|
||
// Wait — dst_valid should assert but data shouldn't be consumed
|
||
begin : c4_wait_valid
|
||
integer wait_cnt;
|
||
for (wait_cnt = 0; wait_cnt < 30; wait_cnt = wait_cnt + 1) begin
|
||
@(posedge m3_dst_clk); #1;
|
||
if (m3_dst_valid) disable c4_wait_valid;
|
||
end
|
||
end
|
||
check(m3_dst_valid === 1'b1, "M3: dst_valid asserts even without dst_ready");
|
||
check(m3_dst_data === 32'hCAFEBABE, "M3: Correct data held during backpressure");
|
||
|
||
// src should NOT be ready (busy with in-flight transfer)
|
||
check(m3_src_ready === 1'b0, "M3: src_ready = 0 during backpressure");
|
||
|
||
// Now assert dst_ready — transfer should complete
|
||
m3_dst_ready = 1;
|
||
begin : c4_wait_done
|
||
integer wait_cnt;
|
||
for (wait_cnt = 0; wait_cnt < 30; wait_cnt = wait_cnt + 1) begin
|
||
@(posedge m3_src_clk); #1;
|
||
if (m3_src_ready) disable c4_wait_done;
|
||
end
|
||
end
|
||
check(m3_src_ready === 1'b1, "M3: src_ready reasserts after backpressure release");
|
||
|
||
// ── C5: Data integrity with edge-case values ───────────
|
||
$display("\n--- C5: Edge-Case Values ---");
|
||
m3_reset_n = 0;
|
||
#200;
|
||
m3_reset_n = 1;
|
||
@(posedge m3_src_clk);
|
||
m3_dst_ready = 1;
|
||
|
||
begin : c5_block
|
||
reg [31:0] edge_vals [0:3];
|
||
reg [31:0] edge_recv [0:3];
|
||
integer tx_idx, rx_idx, wait_cnt;
|
||
reg all_match;
|
||
reg src_wait_done, dst_wait_done;
|
||
|
||
edge_vals[0] = 32'h00000000;
|
||
edge_vals[1] = 32'hFFFFFFFF;
|
||
edge_vals[2] = 32'h80000000;
|
||
edge_vals[3] = 32'h00000001;
|
||
|
||
rx_idx = 0;
|
||
|
||
for (tx_idx = 0; tx_idx < 4; tx_idx = tx_idx + 1) begin
|
||
// Wait for src_ready
|
||
src_wait_done = 0;
|
||
for (wait_cnt = 0; wait_cnt < 50 && !src_wait_done; wait_cnt = wait_cnt + 1) begin
|
||
@(posedge m3_src_clk); #1;
|
||
if (m3_src_ready) src_wait_done = 1;
|
||
end
|
||
|
||
m3_src_data = edge_vals[tx_idx];
|
||
m3_src_valid = 1;
|
||
@(posedge m3_src_clk); #1;
|
||
m3_src_valid = 0;
|
||
|
||
dst_wait_done = 0;
|
||
for (wait_cnt = 0; wait_cnt < 50 && !dst_wait_done; wait_cnt = wait_cnt + 1) begin
|
||
@(posedge m3_dst_clk); #1;
|
||
if (m3_dst_valid) begin
|
||
edge_recv[rx_idx] = m3_dst_data;
|
||
rx_idx = rx_idx + 1;
|
||
dst_wait_done = 1;
|
||
end
|
||
end
|
||
end
|
||
|
||
all_match = 1;
|
||
for (i = 0; i < 4; i = i + 1) begin
|
||
if (i < rx_idx && edge_recv[i] !== edge_vals[i]) begin
|
||
all_match = 0;
|
||
$display(" [WARN] Edge val[%0d]: got 0x%08x, exp 0x%08x",
|
||
i, edge_recv[i], edge_vals[i]);
|
||
end
|
||
end
|
||
check(rx_idx == 4, "M3: All 4 edge-case values received");
|
||
check(all_match, "M3: Edge-case values (0x0, 0xFFFF, 0x8000, 0x1) correct");
|
||
end
|
||
|
||
// ════════════════════════════════════════════════════════
|
||
// Summary
|
||
// ════════════════════════════════════════════════════════
|
||
$display("");
|
||
$display("========================================");
|
||
$display(" CDC MODULES TESTBENCH RESULTS");
|
||
$display(" PASSED: %0d / %0d", pass_count, test_num);
|
||
$display(" FAILED: %0d / %0d", fail_count, test_num);
|
||
if (fail_count == 0)
|
||
$display(" ** ALL TESTS PASSED **");
|
||
else
|
||
$display(" ** SOME TESTS FAILED **");
|
||
$display("========================================");
|
||
$display("");
|
||
|
||
#100;
|
||
$finish;
|
||
end
|
||
|
||
endmodule
|