 Serhii
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48b3847256
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fix(scripts): make Vivado TCL scripts portable and update RTL file lists
- Replace hardcoded /home/jason-stone/ paths with [info script]-relative
path resolution in all 9 scripts (build17-21, insert_ila_probes,
program_fpga, ila_capture, run_cdc_and_netlist)
- Point constraint references at tracked XDC files instead of
untracked synth_only.xdc
- Remove six phantom RTL entries (chirp_lut_init.v, fft_1024_forward.v,
fft_1024_inverse.v, level_shifter_interface.v, lvds_to_cmos_400m.v,
usb_packet_analyzer.v)
- Add six existing modules to file lists (rx_gain_control.v,
mti_canceller.v, cfar_ca.v, fpga_self_test.v, xfft_16.v,
adc_clk_mmcm.v)
Closes #38
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2026-04-06 22:53:42 +03:00 |
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Jason
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19284ac277
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Build 21 docs + TCL fix: WNS +0.156ns, 139 DSP, tag v0.1.4-build21
Build 21 Vivado results extracted and documented:
- WNS +0.156 ns, WHS +0.064 ns, WPWS +0.361 ns (all timing met)
- 6,192 LUTs (4.6%), 9,064 FFs (3.4%), 16 BRAM (4.4%), 139 DSP48E1 (18.8%)
- Total power: 0.732 W
- Barrel-shift twiddle freed 1 DSP (140 -> 139) as expected
- TCL script fix: wrap check_timing in catch (Vivado 2025.2 bug)
- Updated release-notes.html, implementation-log.html, reports.html
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2026-03-20 02:21:33 +02:00 |
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