Jason
49eb6169b6
- Expand ft601_be from [1:0] to [3:0] across RTL, top-level, testbenches, and XDC (uncomment be[2:3] pin assignments B21/A21) - Fix NCO XSim testbench: correct reset check (0x7FFF not 0), add pipeline warmup and sample skip for DSP48E1 quadrature test - All local regression tests pass (39/39 USB, 10/10 integration, all co-sim)
79 lines
3.1 KiB
Markdown
79 lines
3.1 KiB
Markdown
# AERIS-10 FPGA Constraint Files
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## Two Targets
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| File | Device | Package | Purpose |
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|------|--------|---------|---------|
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| `xc7a50t_ftg256.xdc` | XC7A50T-2FTG256I | FTG256 (256-ball BGA) | Upstream author's board (copy of `cntrt.xdc`) |
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| `xc7a200t_fbg484.xdc` | XC7A200T-2FBG484I | FBG484 (484-ball BGA) | Production board (new PCB design) |
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## Why Two Files
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The upstream prototype uses a smaller XC7A50T in an FTG256 package. The production
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AERIS-10 radar migrates to the XC7A200T for more logic, BRAM, and DSP resources.
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The two devices have completely different packages and pin names, so each needs its
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own constraint file. Both files constrain the same RTL top module (`radar_system_top.v`).
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## Bank Voltage Assignments
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### XC7A50T-FTG256 (Upstream)
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| Bank | VCCO | Signals |
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|------|------|---------|
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| 0 | 3.3V | JTAG, flash CS |
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| 14 | 3.3V | ADC LVDS (LVDS_33), SPI flash |
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| 15 | 3.3V | DAC, clocks, STM32 3.3V SPI, DIG bus |
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| 34 | 1.8V | ADAR1000 control, SPI 1.8V side |
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| 35 | 3.3V | Unused (no signal connections) |
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### XC7A200T-FBG484 (Production)
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| Bank | VCCO | Used/Avail | Signals |
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|------|------|------------|---------|
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| 13 | 3.3V | 17/35 | Debug overflow (doppler bins, range bins, status) |
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| 14 | 2.5V | 19/50 | ADC LVDS_25 + DIFF_TERM, ADC power-down |
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| 15 | 3.3V | 27/50 | System clocks (100M, 120M), DAC, RF, STM32 3.3V SPI, DIG bus |
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| 16 | 3.3V | 50/50 | FT601 USB 3.0 (32-bit data + byte enable + control) |
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| 34 | 1.8V | 19/50 | ADAR1000 beamformer control, SPI 1.8V side |
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| 35 | 3.3V | 50/50 | Status outputs (beam position, chirp, doppler data bus) |
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## Signal Differences Between Targets
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| Signal | Upstream (FTG256) | Production (FBG484) |
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|--------|-------------------|---------------------|
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| FT601 USB | Unwired (chip placed, no nets) | Fully wired, Bank 16 |
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| `dac_clk` | Not connected (DAC clocked by AD9523 directly) | Routed, FPGA drives DAC |
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| `ft601_be` width | `[1:0]` in upstream RTL | `[3:0]` (RTL updated) |
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| ADC LVDS standard | LVDS_33 (3.3V bank) | LVDS_25 (2.5V bank, better quality) |
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| Status/debug outputs | No physical pins (commented out) | All routed to Banks 35 + 13 |
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## How to Select in Vivado
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In the Vivado project, only one XDC should be active at a time:
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1. Add both files to the project: `File > Add Sources > Add Constraints`
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2. In the Sources panel, right-click the XDC you do NOT want and select
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`Set File Properties > Enabled = false` (or remove it from the active
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constraint set)
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3. Alternatively, use two separate constraint sets and switch between them
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For TCL-based flows:
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```tcl
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# For production target:
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read_xdc constraints/xc7a200t_fbg484.xdc
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# For upstream target:
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read_xdc constraints/xc7a50t_ftg256.xdc
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```
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## Notes
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- The production XDC pin assignments are **recommended** for the new PCB.
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The PCB designer should follow this allocation.
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- Bank 16 (FT601) is fully utilized at 50/50 pins. No room for expansion
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on that bank.
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- Bank 35 (status/debug) is also at capacity (50/50). Additional debug
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signals should use Bank 13 spare pins (18 remaining).
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- Clock inputs are placed on MRCC (Multi-Region Clock Capable) pins to
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ensure proper clock tree access.
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