153 lines
6.2 KiB
Markdown
153 lines
6.2 KiB
Markdown
# AERIS-10 FPGA Constraint Files
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## Four Targets
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| File | Device | Package | Purpose |
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|------|--------|---------|---------|
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| `xc7a50t_ftg256.xdc` | XC7A50T-2FTG256I | FTG256 (256-ball BGA) | Upstream author's board (copy of `cntrt.xdc`) |
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| `xc7a200t_fbg484.xdc` | XC7A200T-2FBG484I | FBG484 (484-ball BGA) | Production board (new PCB design) |
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| `te0712_te0701_minimal.xdc` | XC7A200T-2FBG484I | FBG484 (484-ball BGA) | Trenz dev split target (minimal clock/reset + LEDs/status) |
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| `te0713_te0701_minimal.xdc` | XC7A200T-2FBG484C | FBG484 (484-ball BGA) | Trenz alternate SoM target (minimal clock + FMC status outputs) |
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## Why Four Files
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The upstream prototype uses a smaller XC7A50T in an FTG256 package. The production
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AERIS-10 radar migrates to the XC7A200T for more logic, BRAM, and DSP resources.
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The two devices have completely different packages and pin names, so each needs its
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own constraint file.
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The Trenz TE0712/TE0701 path uses the same FPGA part as production but different board
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pinout and peripherals. The dev target is split into its own top wrapper
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(`radar_system_top_te0712_dev.v`) and minimal constraints file to avoid accidental mixing
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of production pin assignments during bring-up.
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The Trenz TE0713/TE0701 path supports situations where TE0712 lead time is prohibitive.
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TE0713 uses XC7A200T-2FBG484C (commercial temp grade) and requires separate clock mapping,
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so it has its own dev top and XDC.
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## Bank Voltage Assignments
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### XC7A50T-FTG256 (Upstream)
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| Bank | VCCO | Signals |
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|------|------|---------|
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| 0 | 3.3V | JTAG, flash CS |
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| 14 | 3.3V | ADC LVDS (LVDS_33), SPI flash |
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| 15 | 3.3V | DAC, clocks, STM32 3.3V SPI, DIG bus |
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| 34 | 1.8V | ADAR1000 control, SPI 1.8V side |
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| 35 | 3.3V | Unused (no signal connections) |
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### XC7A200T-FBG484 (Production)
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| Bank | VCCO | Used/Avail | Signals |
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|------|------|------------|---------|
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| 13 | 3.3V | 17/35 | Debug overflow (doppler bins, range bins, status) |
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| 14 | 2.5V | 19/50 | ADC LVDS_25 + DIFF_TERM, ADC power-down |
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| 15 | 3.3V | 27/50 | System clocks (100M, 120M), DAC, RF, STM32 3.3V SPI, DIG bus |
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| 16 | 3.3V | 50/50 | FT601 USB 3.0 (32-bit data + byte enable + control) |
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| 34 | 1.8V | 19/50 | ADAR1000 beamformer control, SPI 1.8V side |
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| 35 | 3.3V | 50/50 | Status outputs (beam position, chirp, doppler data bus) |
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## Signal Differences Between Targets
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| Signal | Upstream (FTG256) | Production (FBG484) |
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|--------|-------------------|---------------------|
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| FT601 USB | Unwired (chip placed, no nets) | Fully wired, Bank 16 |
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| `dac_clk` | Not connected (DAC clocked by AD9523 directly) | Routed, FPGA drives DAC |
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| `ft601_be` width | `[1:0]` in upstream RTL | `[3:0]` (RTL updated) |
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| ADC LVDS standard | LVDS_33 (3.3V bank) | LVDS_25 (2.5V bank, better quality) |
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| Status/debug outputs | No physical pins (commented out) | All routed to Banks 35 + 13 |
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## How to Select in Vivado
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In the Vivado project, only one target XDC should be active at a time:
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1. Add both files to the project: `File > Add Sources > Add Constraints`
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2. In the Sources panel, right-click the XDC you do NOT want and select
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`Set File Properties > Enabled = false` (or remove it from the active
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constraint set)
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3. Alternatively, use two separate constraint sets and switch between them
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For TCL-based flows:
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```tcl
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# For production target:
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read_xdc constraints/xc7a200t_fbg484.xdc
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# For upstream target:
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read_xdc constraints/xc7a50t_ftg256.xdc
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# For Trenz TE0712/TE0701 split target:
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read_xdc constraints/te0712_te0701_minimal.xdc
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# For Trenz TE0713/TE0701 split target:
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read_xdc constraints/te0713_te0701_minimal.xdc
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```
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## Top Modules by Target
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| Target | Top module | Notes |
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|--------|------------|-------|
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| Upstream FTG256 | `radar_system_top` | Legacy board support |
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| Production FBG484 | `radar_system_top` | Main AERIS-10 board |
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| Trenz TE0712/TE0701 | `radar_system_top_te0712_dev` | Minimal bring-up wrapper while pinout/peripherals are migrated |
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| Trenz TE0713/TE0701 | `radar_system_top_te0713_dev` | Alternate SoM wrapper (TE0713 clock mapping) |
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## Trenz Split Status
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- `constraints/te0712_te0701_minimal.xdc` currently includes verified TE0712 pins:
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- `clk_100m` -> `R4` (TE0712 `CLK1B[0]`, 50 MHz source)
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- `reset_n` -> `T3` (TE0712 reset pin)
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- `user_led` and `system_status` are now mapped to TE0701 FMC LA lines through TE0712 B16
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package pins (GPIO export path, not TE0701 onboard LED D1..D8).
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- Temporary `NSTD-1`/`UCIO-1` severity downgrades were removed after pin assignment.
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### Current GPIO Export Map
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| Port | TE0712 package pin | TE0712 net | TE0701 FMC net |
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|------|---------------------|------------|----------------|
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| `user_led[0]` | `A19` | `B16_L17_N` | `FMC_LA14_N` |
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| `user_led[1]` | `A18` | `B16_L17_P` | `FMC_LA14_P` |
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| `user_led[2]` | `F20` | `B16_L18_N` | `FMC_LA13_N` |
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| `user_led[3]` | `F19` | `B16_L18_P` | `FMC_LA13_P` |
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| `system_status[0]` | `F18` | `B16_L15_P` | `FMC_LA5_N` |
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| `system_status[1]` | `E18` | `B16_L15_N` | `FMC_LA5_P` |
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| `system_status[2]` | `C22` | `B16_L20_P` | `FMC_LA6_N` |
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| `system_status[3]` | `B22` | `B16_L20_N` | `FMC_LA6_P` |
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Note: FMC direction/N/P labeling must be validated against TE0701 connector orientation
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and I/O Planner before final hardware sign-off.
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## Trenz Batch Build
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Use the dedicated script for the split dev target:
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```bash
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vivado -mode batch -source scripts/build_te0712_dev.tcl
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# TE0713/TE0701 target
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vivado -mode batch -source scripts/build_te0713_dev.tcl
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```
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Outputs:
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- Project directory: `vivado_te0712_dev/`
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- Reports: `vivado_te0712_dev/reports/`
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- Top module: `radar_system_top_te0712_dev`
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- Constraint file: `constraints/te0712_te0701_minimal.xdc`
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TE0713 outputs:
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- Project directory: `vivado_te0713_dev/`
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- Reports: `vivado_te0713_dev/reports/`
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- Top module: `radar_system_top_te0713_dev`
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- Constraint file: `constraints/te0713_te0701_minimal.xdc`
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## Notes
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- The production XDC pin assignments are **recommended** for the new PCB.
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The PCB designer should follow this allocation.
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- Bank 16 (FT601) is fully utilized at 50/50 pins. No room for expansion
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on that bank.
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- Bank 35 (status/debug) is also at capacity (50/50). Additional debug
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signals should use Bank 13 spare pins (18 remaining).
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- Clock inputs are placed on MRCC (Multi-Region Clock Capable) pins to
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ensure proper clock tree access.
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