5499827ab7
FMC LPC dev build for TE0713/TE0701 + UMFT601X-B stack. Fixed timing closure: replaced set_output_delay with set_max_delay -datapath_only to eliminate false IBUF+BUFG clock skew penalty on source-synchronous outputs. Removed erroneous set_input_delay on output-only ft601_be[*]. Added IOB packing for siwu_n, false paths for async GPIO/reset/wakeup. Strategy: Performance_ExplorePostRoutePhysOpt. Results: WNS +0.059 ns, WHS +0.121 ns, DRC 0 errors, 0 failing endpoints. Bitstream: docs/artifacts/te0713-te0701-umft601x-dev-2026-03-21.bit
343 lines
17 KiB
Tcl
343 lines
17 KiB
Tcl
# ============================================================================
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# AERIS-10 FT601 via FMC LPC: TE0713 + TE0701 + UMFT601X-B
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# ============================================================================
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# Target: XC7A200T-2FBG484C (TE0713-03) on TE0701-06 carrier
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# FT601 board: UMFT601X-B (32-bit FT601 eval, FMC LPC)
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#
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# Signal chain:
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# FPGA ball → TE0713 B2B → TE0701 carrier → FMC LPC J10 → UMFT601X-B FT601
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#
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# Bank split:
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# Bank 15 (VCCO = VIOTB): DATA[31:0], D_CLK (33 pins)
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# Bank 16 (VCCO = VIOTB): BE_N[3:0], OE_N, RD_N, WR_N, TXE_N, RXF_N,
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# SIWU_N, RESET_N, WAKEUP_N, GPIO0, GPIO1 (14 pins)
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#
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# CRITICAL SETUP:
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# 1. TE0701 VIOTB must be set to 3.3V (jumper J16/J17/J21 configuration)
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# OR FMC_VADJ (DIP S4) set to 3.3V with VIOTB routed to FMC_VADJ
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# 2. UMFT601X-B VCCIO jumper set to 3.3V
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# 3. This XDC replaces the FT601 section of xc7a200t_fbg484.xdc (production
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# PCB pinout) — do NOT use both simultaneously
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#
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# Source mapping:
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# UMFT601X-B: DS_UMFT60x.pdf Table 2.7 (CN4 FMC connector, FT601 column)
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# TE0701→TE0713: TE0701_FMC_PINOUT.xlsx (FMC J10 → B2B → FPGA pin)
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#
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# Verified: 2026-03-19
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# ============================================================================
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# --------------------------------------------------------------------------
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# FT601 Clock Input — 100 MHz from FT601 chip
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# FMC: LA18_P_CC → FPGA J20 (Bank 15, IO_L11P_T1_SRCC_15)
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# SRCC is sufficient for 100 MHz FIFO clock via IBUF→BUFG
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# --------------------------------------------------------------------------
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set_property PACKAGE_PIN J20 [get_ports {ft601_clk_in}]
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set_property IOSTANDARD LVCMOS33 [get_ports {ft601_clk_in}]
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create_clock -name ft601_clk_in -period 10.000 [get_ports {ft601_clk_in}]
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set_input_jitter [get_clocks ft601_clk_in] 0.100
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# --------------------------------------------------------------------------
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# FT601 Data Bus [31:0] — bidirectional, 3.3V LVCMOS
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# All data pins in Bank 15
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# --------------------------------------------------------------------------
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# FMC LA32_N → L21
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set_property PACKAGE_PIN L21 [get_ports {ft601_data[0]}]
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# FMC LA33_N → N20
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set_property PACKAGE_PIN N20 [get_ports {ft601_data[1]}]
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# FMC LA32_P → M21
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set_property PACKAGE_PIN M21 [get_ports {ft601_data[2]}]
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# FMC LA33_P → M20
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set_property PACKAGE_PIN M20 [get_ports {ft601_data[3]}]
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# FMC LA30_N → M13
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set_property PACKAGE_PIN M13 [get_ports {ft601_data[4]}]
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# FMC LA31_N → N22
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set_property PACKAGE_PIN N22 [get_ports {ft601_data[5]}]
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# FMC LA30_P → L13
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set_property PACKAGE_PIN L13 [get_ports {ft601_data[6]}]
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# FMC LA31_P → M22
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set_property PACKAGE_PIN M22 [get_ports {ft601_data[7]}]
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# FMC LA28_N → H18
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set_property PACKAGE_PIN H18 [get_ports {ft601_data[8]}]
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# FMC LA29_N → K17
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set_property PACKAGE_PIN K17 [get_ports {ft601_data[9]}]
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# FMC LA28_P → H17
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set_property PACKAGE_PIN H17 [get_ports {ft601_data[10]}]
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# FMC LA29_P → J17
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set_property PACKAGE_PIN J17 [get_ports {ft601_data[11]}]
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# FMC LA24_N → L15
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set_property PACKAGE_PIN L15 [get_ports {ft601_data[12]}]
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# FMC LA25_N → J15
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set_property PACKAGE_PIN J15 [get_ports {ft601_data[13]}]
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# FMC LA24_P → L14
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set_property PACKAGE_PIN L14 [get_ports {ft601_data[14]}]
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# FMC LA25_P → H15
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set_property PACKAGE_PIN H15 [get_ports {ft601_data[15]}]
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# FMC LA27_N → G13
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set_property PACKAGE_PIN G13 [get_ports {ft601_data[16]}]
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# FMC LA26_N → G15
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set_property PACKAGE_PIN G15 [get_ports {ft601_data[17]}]
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# FMC LA27_P → H13
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set_property PACKAGE_PIN H13 [get_ports {ft601_data[18]}]
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# FMC LA26_P → G16
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set_property PACKAGE_PIN G16 [get_ports {ft601_data[19]}]
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# FMC LA21_N → G18
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set_property PACKAGE_PIN G18 [get_ports {ft601_data[20]}]
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# FMC LA22_N → L18
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set_property PACKAGE_PIN L18 [get_ports {ft601_data[21]}]
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# FMC LA21_P → G17
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set_property PACKAGE_PIN G17 [get_ports {ft601_data[22]}]
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# FMC LA22_P → M18
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set_property PACKAGE_PIN M18 [get_ports {ft601_data[23]}]
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# FMC LA23_N → H14
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set_property PACKAGE_PIN H14 [get_ports {ft601_data[24]}]
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# FMC LA23_P → J14
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set_property PACKAGE_PIN J14 [get_ports {ft601_data[25]}]
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# FMC LA19_N → N18
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set_property PACKAGE_PIN N18 [get_ports {ft601_data[26]}]
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# FMC LA19_P → N19
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set_property PACKAGE_PIN N19 [get_ports {ft601_data[27]}]
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# FMC LA20_N → K14
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set_property PACKAGE_PIN K14 [get_ports {ft601_data[28]}]
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# FMC LA20_P → K13
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set_property PACKAGE_PIN K13 [get_ports {ft601_data[29]}]
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# FMC LA17_N_CC → H19
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set_property PACKAGE_PIN H19 [get_ports {ft601_data[30]}]
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# FMC LA17_P_CC → J19
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set_property PACKAGE_PIN J19 [get_ports {ft601_data[31]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {ft601_data[*]}]
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set_property SLEW FAST [get_ports {ft601_data[*]}]
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set_property DRIVE 8 [get_ports {ft601_data[*]}]
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# --------------------------------------------------------------------------
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# FT601 Byte Enable [3:0] — active-low, bidirectional
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# BE_N[0:1] in Bank 16, BE_N[2:3] in Bank 16
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# --------------------------------------------------------------------------
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# FMC LA15_N → B20
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set_property PACKAGE_PIN B20 [get_ports {ft601_be[0]}]
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# FMC LA15_P → A20
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set_property PACKAGE_PIN A20 [get_ports {ft601_be[1]}]
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# FMC LA09_N → D16
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set_property PACKAGE_PIN D16 [get_ports {ft601_be[2]}]
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# FMC LA09_P → E16
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set_property PACKAGE_PIN E16 [get_ports {ft601_be[3]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {ft601_be[*]}]
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set_property SLEW FAST [get_ports {ft601_be[*]}]
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set_property DRIVE 8 [get_ports {ft601_be[*]}]
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# --------------------------------------------------------------------------
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# FT601 Control Signals — active-low strobes (Bank 16)
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# --------------------------------------------------------------------------
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# FMC LA00_P_CC → C17 (OE_N)
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set_property PACKAGE_PIN C17 [get_ports {ft601_oe_n}]
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# FMC LA00_N_CC → D17 (RD_N)
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set_property PACKAGE_PIN D17 [get_ports {ft601_rd_n}]
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# FMC LA08_P → E13 (WR_N)
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set_property PACKAGE_PIN E13 [get_ports {ft601_wr_n}]
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# FMC LA08_N → E14 (SIWU_N)
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set_property PACKAGE_PIN E14 [get_ports {ft601_siwu_n}]
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set_property IOSTANDARD LVCMOS33 [get_ports {ft601_oe_n}]
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set_property IOSTANDARD LVCMOS33 [get_ports {ft601_rd_n}]
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set_property IOSTANDARD LVCMOS33 [get_ports {ft601_wr_n}]
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set_property IOSTANDARD LVCMOS33 [get_ports {ft601_siwu_n}]
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set_property SLEW FAST [get_ports {ft601_oe_n}]
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set_property SLEW FAST [get_ports {ft601_rd_n}]
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set_property SLEW FAST [get_ports {ft601_wr_n}]
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set_property DRIVE 8 [get_ports {ft601_oe_n}]
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set_property DRIVE 8 [get_ports {ft601_rd_n}]
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set_property DRIVE 8 [get_ports {ft601_wr_n}]
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# --------------------------------------------------------------------------
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# FT601 Status Signals (Bank 16)
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# --------------------------------------------------------------------------
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# On UMFT601X-B, FT601 drives TXE_N and RXF_N (active-low) to FPGA.
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# In the production RTL (usb_data_interface.v):
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# - ft601_txe (input, active-HIGH) — FSM checks `!ft601_txe` for "can write"
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# - ft601_txe_n (output reg) — driven to 1, unused (production PCB artifact)
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# - ft601_rxf (input, active-HIGH) — not used in write-only FSM
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# - ft601_rxf_n (output reg) — driven to 1, unused (production PCB artifact)
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#
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# On UMFT601X-B FMC path:
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# - TXE_N from FT601 is LOW when FIFO ready → wire to ft601_txe RTL input
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# - The FSM checks `!ft601_txe`: !LOW = 1 = proceed. Polarity is CORRECT.
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# - ft601_txe_n output and ft601_rxf_n output have no FMC connection (leave
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# unconstrained or tie off in RTL wrapper).
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#
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# FMC LA07_N → E17 (TXE_N from FT601 — wire to RTL port ft601_txe)
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set_property PACKAGE_PIN E17 [get_ports {ft601_txe}]
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# FMC LA07_P → F16 (RXF_N from FT601 — wire to RTL port ft601_rxf)
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set_property PACKAGE_PIN F16 [get_ports {ft601_rxf}]
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set_property IOSTANDARD LVCMOS33 [get_ports {ft601_txe}]
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set_property IOSTANDARD LVCMOS33 [get_ports {ft601_rxf}]
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# --------------------------------------------------------------------------
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# FT601 Reset and Wake (Bank 16) — active-low
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# These are FPGA-to-FT601 control signals, active-low.
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# NOTE: The RTL port ft601_reset_n is an internal synchronized reset INPUT,
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# not a pin output. This FMC pin drives the FT601 chip's RESET_N.
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# Use a separate port name (ft601_chip_reset_n) to avoid collision.
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# --------------------------------------------------------------------------
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# FMC LA10_N → A14 (RESET_N — FPGA drives FT601 reset)
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set_property PACKAGE_PIN A14 [get_ports {ft601_chip_reset_n}]
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# FMC LA10_P → A13 (WAKEUP_N — FPGA drives FT601 wakeup)
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set_property PACKAGE_PIN A13 [get_ports {ft601_wakeup_n}]
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set_property IOSTANDARD LVCMOS33 [get_ports {ft601_chip_reset_n}]
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set_property IOSTANDARD LVCMOS33 [get_ports {ft601_wakeup_n}]
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# --------------------------------------------------------------------------
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# FT601 GPIO (Bank 16) — directly on FMC, active by default on UMFT601X-B
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# --------------------------------------------------------------------------
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# FMC LA14_P → A18 (GPIO0)
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set_property PACKAGE_PIN A18 [get_ports {ft601_gpio0}]
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# FMC LA14_N → A19 (GPIO1)
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set_property PACKAGE_PIN A19 [get_ports {ft601_gpio1}]
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set_property IOSTANDARD LVCMOS33 [get_ports {ft601_gpio0}]
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set_property IOSTANDARD LVCMOS33 [get_ports {ft601_gpio1}]
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# --------------------------------------------------------------------------
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# FT601 Clock Output (forwarded clock to FT601)
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# --------------------------------------------------------------------------
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# NOTE: The UMFT601X-B provides its own 100 MHz clock via D_CLK (ft601_clk_in
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# above). The production design forwards a clock back via ODDR. On the FMC
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# path, there is NO dedicated return-clock LA pin on the UMFT601X-B.
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#
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# The FT601 FIFO interface is source-synchronous from the FT601 perspective:
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# the FT601 provides D_CLK and the FPGA samples/drives data relative to it.
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# For WRITE operations the FPGA drives data on D_CLK edges (no separate
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# forwarded clock needed). ft601_clk_out is NOT used on the FMC path.
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#
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# If the RTL requires ft601_clk_out as a port, constrain it to an unused pin
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# or remove it from the top-level for the FMC build variant.
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# --------------------------------------------------------------------------
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# --------------------------------------------------------------------------
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# FT601 input delays (relative to ft601_clk_in, 100 MHz)
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# FT601 datasheet (245 Sync FIFO mode): Tco max = 7.0 ns, Tco min = 1.0 ns
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# NOTE: ft601_data is bidirectional — input delay applies during READ ops.
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# ft601_be is output-only in this write-only design; no set_input_delay.
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# --------------------------------------------------------------------------
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set_input_delay -clock [get_clocks ft601_clk_in] -max 7.000 [get_ports {ft601_data[*]}]
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set_input_delay -clock [get_clocks ft601_clk_in] -min 1.000 [get_ports {ft601_data[*]}]
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set_input_delay -clock [get_clocks ft601_clk_in] -max 7.000 [get_ports {ft601_txe}]
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set_input_delay -clock [get_clocks ft601_clk_in] -min 1.000 [get_ports {ft601_txe}]
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set_input_delay -clock [get_clocks ft601_clk_in] -max 7.000 [get_ports {ft601_rxf}]
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set_input_delay -clock [get_clocks ft601_clk_in] -min 1.000 [get_ports {ft601_rxf}]
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# ft601_be[*] is output-only — removed erroneous set_input_delay (was causing
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# critical warnings and dropped constraints in previous build)
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# --------------------------------------------------------------------------
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# FT601 output timing — source-synchronous, datapath-only constraints
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# --------------------------------------------------------------------------
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# The FT601 provides its own 100 MHz clock (D_CLK) and samples data on
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# the next rising edge of that same clock. The FPGA receives D_CLK through
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# IBUF→BUFG (~5 ns insertion), but this insertion delay is COMMON to both
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# the data launch (register clocked by BUFG output) and the data capture
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# (FT601 sampling on the same physical clock edge).
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#
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# Using set_output_delay with the real clock creates a false ~5 ns skew
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# penalty. Using a virtual clock doesn't help because Vivado still sees
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# the IBUF+BUFG insertion on the source side.
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#
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# Instead, we use set_max_delay -datapath_only to constrain the
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# register-to-pad delay directly. The budget is:
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# Tperiod(10 ns) - Tsu(2.0 ns) - Tboard_margin(0.5 ns) = 7.5 ns
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# This ensures data arrives at the FT601 pad with 2.5 ns margin before
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# the next clock edge.
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#
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# For hold (min delay): We use set_min_delay. The FT601 Th = 0.5 ns.
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# The data must not change until 0.5 ns after the CURRENT clock edge.
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# Since the register launches on the clock edge and the pad delay is
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# always positive (>= 1 ns), hold is inherently met. We set min = 0
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# to be safe.
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# --------------------------------------------------------------------------
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# Remove any output_delay on these ports (clean slate — the constraints
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# below supersede them)
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# Data bus
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set_max_delay -datapath_only -from [get_clocks ft601_clk_in] -to [get_ports {ft601_data[*]}] 7.500
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set_min_delay -from [get_clocks ft601_clk_in] -to [get_ports {ft601_data[*]}] 0.000
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# Byte enable
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set_max_delay -datapath_only -from [get_clocks ft601_clk_in] -to [get_ports {ft601_be[*]}] 7.500
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set_min_delay -from [get_clocks ft601_clk_in] -to [get_ports {ft601_be[*]}] 0.000
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# Write strobe
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set_max_delay -datapath_only -from [get_clocks ft601_clk_in] -to [get_ports {ft601_wr_n}] 7.500
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set_min_delay -from [get_clocks ft601_clk_in] -to [get_ports {ft601_wr_n}] 0.000
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# Read strobe
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set_max_delay -datapath_only -from [get_clocks ft601_clk_in] -to [get_ports {ft601_rd_n}] 7.500
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set_min_delay -from [get_clocks ft601_clk_in] -to [get_ports {ft601_rd_n}] 0.000
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# Output enable
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set_max_delay -datapath_only -from [get_clocks ft601_clk_in] -to [get_ports {ft601_oe_n}] 7.500
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set_min_delay -from [get_clocks ft601_clk_in] -to [get_ports {ft601_oe_n}] 0.000
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# --------------------------------------------------------------------------
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# Note: Input delays still reference ft601_clk_in (correct for inputs,
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# where the FT601 drives data relative to its clock and the FPGA samples
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# after IBUF+BUFG insertion — the pessimistic direction Vivado handles
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# correctly).
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# --------------------------------------------------------------------------
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# --------------------------------------------------------------------------
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# IOB packing for timing — same strategy as production XDC
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# Use -quiet because register names depend on synthesis elaboration;
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# a -quiet miss is non-fatal, but the constraint logs should be checked.
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# --------------------------------------------------------------------------
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set_property -quiet IOB TRUE [get_cells -hierarchical -filter {NAME =~ *usb_inst/ft601_data_out_reg*}]
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set_property -quiet IOB TRUE [get_cells -hierarchical -filter {NAME =~ *usb_inst/ft601_be_reg*}]
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set_property -quiet IOB TRUE [get_cells -hierarchical -filter {NAME =~ *usb_inst/ft601_wr_n_reg*}]
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set_property -quiet IOB TRUE [get_cells -hierarchical -filter {NAME =~ *usb_inst/ft601_rd_n_reg*}]
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set_property -quiet IOB TRUE [get_cells -hierarchical -filter {NAME =~ *usb_inst/ft601_oe_n_reg*}]
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set_property -quiet IOB TRUE [get_cells -hierarchical -filter {NAME =~ *usb_inst/ft601_siwu_n_reg*}]
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# --------------------------------------------------------------------------
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# Async / false paths — chip reset and wakeup are not timing-critical
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# --------------------------------------------------------------------------
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set_false_path -to [get_ports {ft601_chip_reset_n}]
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set_false_path -to [get_ports {ft601_wakeup_n}]
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set_false_path -to [get_ports {ft601_gpio0}]
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set_false_path -to [get_ports {ft601_gpio1}]
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# --------------------------------------------------------------------------
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# NOTES ON RTL ADAPTATION FOR FMC BUILD
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# --------------------------------------------------------------------------
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# The production RTL (usb_data_interface.v) has these ports that need
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# handling for the FMC dev build:
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#
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# 1. ft601_clk_out (output) — ODDR forwarded clock. No FMC return path
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# on UMFT601X-B. Leave unconnected or assign to an unused Bank 16 pin.
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#
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# 2. ft601_txe_n (output reg) — Production PCB artifact. Driven to 1,
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# never functionally used. Leave unconstrained (no FMC connection).
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#
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# 3. ft601_rxf_n (output reg) — Same as txe_n. Leave unconstrained.
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#
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# 4. ft601_srb[1:0] (input) — FIFO buffer select. Not on UMFT601X-B FMC.
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# Tie to 2'b00 in RTL wrapper or via pulldown.
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#
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# 5. ft601_swb[1:0] (input) — Same as srb. Tie to 2'b00.
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#
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# 6. ft601_txe (input) — Wired to UMFT601X-B TXE_N (active-low from FT601).
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# Polarity works: FSM checks `!ft601_txe` → !LOW=1 → proceed when ready.
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#
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# 7. ft601_rxf (input) — Wired to UMFT601X-B RXF_N (active-low from FT601).
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# Not used in current write-only FSM but correct for future read path.
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#
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# 8. ft601_reset_n (input in RTL at port level, but also used as
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# ft601_reset_n on UMFT601X-B FMC LA10_N). The XDC above constrains
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# ft601_reset_n — this is an OUTPUT from FPGA to reset the FT601 chip,
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# not the RTL's synchronized reset input. The RTL's ft601_reset_n input
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# should be driven by internal logic (e.g., system reset synchronized to
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# ft601_clk_in). The FMC pin ft601_reset_n should be a separate port.
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#
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# RECOMMENDED: Create a thin FMC wrapper module that:
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# - Instantiates usb_data_interface with existing port names
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# - Ties ft601_srb/ft601_swb to 2'b00
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# - Leaves ft601_txe_n/ft601_rxf_n unconnected
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# - Assigns ft601_clk_out to an unused pin or removes it
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# - Adds ft601_reset_n, ft601_wakeup_n, ft601_gpio0/1 as new top ports
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# --------------------------------------------------------------------------
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